参数资料
| 型号： | EVAL-ADV7195EB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV7195 |
| 标准包装： | 1 |
| 主要目的： | 视频，视频处理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7195 |
| 主要属性： | 多格式顺序扫描/HDTV 编码器，3 个 11 位 ADC |
| 次要属性： | 内部测试样式发生器，带颜色控制 |
| 已供物品： | 板 |
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ADV7195
DAC TERMINATION AND LAYOUT CONSIDERATIONS
Voltage Reference
The ADV7195 contains an onboard voltage reference. The V REF
pin is normally terminated to V AA through a 0.1 μ F capacitor when
the internal V REF is used. Alternatively, the ADV7195 can be
used with an external V REF (AD589).
Resistor R SET is connected between the R SET pin and AGND
and is used to control the full-scale output current and there-
fore the DAC voltage output levels. For full-scale output, R SET
must have a value of 2470 ? ; R LOAD has a value of 300 ? .
When an input range of 0–1023 is selected, the value of R SET
must be 2820 ? .
The ADV7195 has three analog outputs, corresponding to Y,
Pr, Pb video signals. The DACs must be used with external
buffer circuits in order to provide sufficient current to drive an
output device. Suitable op amps are the AD8009, AD8002,
AD8001, or AD8057. To calculate the output full-scale current
and voltage, the following equations should be used:
V OUT = I OUT × R LOAD
I OUT = [ V REF × k ]/ R SET
k = 5.66, for I/P Ranges 64–940, 64–960, O/P Standards
EIA- 770.1–3
k = 6.46 , F CI Input Ranges 0–1023 , Output Standard
RS- 170/343 A
V REF = 1.235 V
PC BOARD LAYOUT CONSIDERATIONS
The ADV7195 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7195, it is imperative
that great care be given to the PC board layout.
The layout should be optimized for lowest noise on the ADV7195
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V AA and AGND, and V DD and DGND pins,
should be kept as short as possible to minimize inductive ringing.
It is recommended that a four-layer printed circuit board be
used. With power and ground planes separating the layer of the
signal carrying traces of the components and solder-side layer.
Placement of components should be considered to separate
noisy circuits such as crystal clocks, high-speed logic circuitry,
and analog circuitry.
There should be a separate analog ground plane (AGND) and
a separate digital ground plane (GND).
Power planes should encompass a digital power plane (V DD )
and an analog power plane (V AA ). The analog power plane
should contain the DACs and all associated circuitry, and the
V REF circuitry.
The digital power plane should contain all logic circuitry. The
analog and digital power planes should be individually con-
nected to the common power plane at one single point through
a suitable filtering device such as a ferrite bead.
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
V AA
10nF
0.1 F
V AA
V AA
0.1 F
24, 35
1, 12
10nF
0.1 F
COMP
V AA
V DD
Cb/Cr0 – Cb/Cr9
DAC A
300
Y OUTPUT
Cr0 – Cr9
Y0 – Y9
DAC B
300
Pr (V) OUTPUT
UNUSED
INPUTS
SHOULD BE
GROUNDED
ADV7195
HSYNC / SYNC
VSYNC /TSYNC
DAC C
300
Pb (U) OUTPUT
V AA
V AA
V AA
4.7k
DV
RESET
SCL
SDA
100
100
5k
5k
MPU BUS
4.7 F
6.3V
V REF
27MHz, 74.25MHz OR
74.1758MHz CLOCK
CLKIN
R SET
2.47k
OR
V AA
ALSB
AGND
GND
2.82k
26, 33
13, 52
4.7k
Figure 57. Circuit Layout
–30 –
REV. A
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