参数资料
| 型号： | EVAL-ADV7195EB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV7195 |
| 标准包装： | 1 |
| 主要目的： | 视频，视频处理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7195 |
| 主要属性： | 多格式顺序扫描/HDTV 编码器，3 个 11 位 ADC |
| 次要属性： | 内部测试样式发生器，带颜色控制 |
| 已供物品： | 板 |
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ADV7195
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Figure 53 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
With these bits it is possible to delay the Y signal with respect to
the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 52 demonstrates this facility.
Color Delay (MR23–MR25)
With these bits it is possible to delay the color signals with
respect to the falling edge of the horizontal sync signal by up to
four pixel clock cycles. Figure 52 demonstrates this facility.
Reserved (MR26–MR27)
A “0” must be written to these bits.
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4-SR0) = 03H)
Figure 54 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
HDTV Enable (MR30)
When this bit is set to “1,” the ADV7195 reverts to HDTV
mode. When set to “0” the ADV7195 reverts to Progressive
Scan Mode (PS mode).
Reserved (MR31–MR32)
A “0” must be written to these bits.
DAC A Control (MR33)
Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
DAC B Control (MR34)
Setting this bit to “1” enables DAC B, otherwise this DAC is
Y DELAY
NO DELAY
MAX DELAY
NO DELAY
Y OUTPUT
powered down.
DAC C Control (MR35)
Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
Reserved (MR36–MR37)
A “0” must be written to these bits.
PrPb DELAY
MAX
DELAY
Figure 52. Y and Color Delay
PrPb OUTPUT
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
MR27 – MR26
COLOR DELAY
Y DELAY
A ZERO MUST
BE WRITTEN
TO THESE BITS
MR25 MR24 MR23
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
MR22 MR21 MR20
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
Figure 53. Mode Register 2
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR37 – MR36
ZERO MUST BE
WRITTEN TO
THESE BITS
DAC B CONTROL
MR34
0 POWER-DOWN
1 NORMAL
MR32 – MR31
ZERO MUST BE
WRITTEN TO
THESE BITS
HDTV ENABLE
MR30
0 DISABLE
1 ENABLE
DAC C CONTROL
MR35
0 POWER-DOWN
1 NORMAL
DAC A CONTROL
MR33
0 POWER-DOWN
1 NORMAL
Figure 54. Mode Register 3
–28 –
REV. A
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