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参数资料
| 型号： | FAN5019MTCX_NL |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封装： | LEAD FREE, TSSOP-28 |
| 文件页数： | 10/30页 |
| 文件大小： | 781K |
| 代理商： | FAN5019MTCX_NL |
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FAN5019
PRODUCT SPECIFICATION
18
REV. 1.0.7 1/5/04
Power Good Monitoring
The Power Good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indi-
cates that the output voltage is within the nominal limits
specied in the specications table based on the VID volt-
age setting. PWRGD will go low if the output voltage is out-
side of this specied range. PWRGD is blanked during a
VID OTF event for a period of 250s to prevent false signals
during the time the output is changing.
Output Crowbar
As part of the protection for the load and output components
of the supply, the PWM outputs will be driven low (turning
on the low-side MOSFETs) when the output voltage exceeds
the upper Power Good threshold. This crowbar action will
stop once the output voltage has fallen below the release
threshold of approximately 550mV.
Turning on the low-side MOSFETs pulls down the output
voltage as the reverse current builds up in the inductors.
If the output overvoltage is due to a short of the high side
MOSFET, this action will current limit the input supply
or blow its fuse, protecting the microprocessor from
destruction.
Output Enable and UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher then its
logic threshold for the FAN5019 to begin switching. If
UVLO is less than the threshold or the EN pin is a logic low,
the FAN5019 is disabled. This holds the PWM outputs at
ground, shorts the DELAY capacitor to ground, and holds
the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be con-
nected to the output disable pins of the FAN5009 drivers.
Because ILIMIT is grounded, this disables the drivers such
that both DRVH and DRVL are grounded. This feature is
important to prevent discharging of the output capacitors
when the controller is shut off. If the driver outputs were not
disabled, then a negative voltage could be generated on the
output due to the high current discharge of the output
capacitors through the inductors.
Application Information
The design parameters for a typical Intel VRD10.x
compliant CPU application are as follows:
Input voltage (VIN) = 12V
VID setting voltage (VVID) = 1.500V
Duty cycle (D) = 0.125
Nominal output voltage at no load (VONL) = 1.480V
Nominal output voltage at 65 A load (VOFL) = 1.3955V
Static output voltage drop based on a 1.3 m
load line
(RO) from no load to full load
(VD) = VONL – VOFL = 1.480V – 1.3955V = 84.5mV
Maximum Output Current (IO) = 65A
Maximum Output Current Step (
IO) = 60A
Number of Phases (n) = 3
Switching frequency per phase (fSW) = 228 kHz
Setting the Clock Frequency
The FAN5019 uses a xed-frequency control architecture
with the frequency being set by an external timing resistor
(RT). The clock frequency and the number of phases deter-
mine the switching frequency per phase, which relates
directly to switching losses and the sizes of the inductors and
input and output capacitors. With n = 3 for three phases, a
clock frequency of 684kHz sets the switching frequency of
each phase, fSW, to 228kHz, which represents a practical
trade-off between the switching losses and the sizes of the
output lter components. TPC 1 shows that to achieve a
684kHz oscillator frequency, the correct value for RT is
301k
. Alternatively, the value for RT can be calculated
using:
where 5.0pF and 110nS are internal IC component values.
For good initial accuracy and frequency stability, it is recom-
mended to use a 1% resistor.
Soft-Start and Current Limit Latch-Off Delay
Times
Because the soft-start and current limit latch off delay
functions share the DELAY pin, these two parameters must
be considered together. The rst step is to set CDLY for the
soft-start ramp. This ramp is generated with a 20A internal
current source. The value of RDLY will have a second order
impact on the soft-start time because it sinks part of the cur-
rent source to ground. However, as long as RDLY is kept
greater than 200k
, this effect is minor. The value for CDLY
can be approximated using:
(
)
nS
pF
f
n
R
SW
T
110
5
1
×
=
(1)
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