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参数资料
| 型号： | FAN5019MTCX_NL |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封装： | LEAD FREE, TSSOP-28 |
| 文件页数： | 16/30页 |
| 文件大小： | 781K |
| 代理商： | FAN5019MTCX_NL |
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PRODUCT SPECIFICATION
FAN5019
REV. 1.0.7 1/5/04
23
Typically, for main MOSFETs, one wants the highest
speed (low CISS) device, but these usually have higher
ON-resistance. One must select a device that meets the total
power dissipation (about 1.5 W for a single D-PAK) when
combining the switching and conduction losses.
For our example, we have selected a Fairchild FD6696 as the
main MOSFET (three total; nMF = 3), with a Ciss = 2058 pF
(max) and RDS(MF) = 15m (max at TJ = 125C) and an
Fairchild FDD6682 as the synchronous MOSFET (six total;
nSF = 6), with Ciss = 2880pF (max) and RDS(SF) = 11.9m
(max at TJ = 125C). The synchronous MOSFET Ciss is less
than 3000 pF, satisfying that requirement. Solving for the
power dissipation per MOSFET at IO = 65A and IR = 8.86A
yields 1.24W for each synchronous MOSFET and 1.62W for
each main MOSFET. These numbers work well considering
there is usually more PCB area available for each main
MOSFET versus each synchronous MOSFET.
One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the QG for
the MOSFETs and is given by the following, where QGMF is
the total gate charge for each main MOSFET and QGSF is the
total gate charge for each synchronous MOSFET:
Also shown is the standby dissipation factor (ICC times the
VCC) for the driver. For the FAN5009, the maximum dissipa-
tion should be less than 400 mW. For our example, with
ICC = 7 mA, QGMF = 24nC (max) and QGSF = 31nC (max),
we nd 202 mW in each driver, which is below the 400 mW
dissipation limit. See the FAN5009 data sheet for more
details.
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the
internal PWM ramp. The value of this resistor is chosen to
provide the best combination of thermal balance, stability,
and transient response. The following expression is used for
determining the optimum value:
where AR is the internal ramp amplier gain, AD is the
current balancing amplier gain, RDS is the total low-side
MOSFET ON-resistance, and CR is the internal ramp
capacitor value. A close standard 1% resistor value is 301k
.
The internal ramp voltage magnitude can be calculated
using:
The size of the internal ramp can be made larger or smaller.
If it is made larger, stability and transient response will
improve, but thermal balance will degrade. Likewise, if the
ramp is made smaller, thermal balance will improve at the
sacrice of transient response and stability. The factor of
three in the denominator of equation 19 sets a ramp size that
gives an optimal balance for good stability, transient
response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds
to the internal ramp to produce the following overall ramp
signal at the PWM input.
For this example, the overall ramp signal is found to be
0.974V.
Current Limit Set Point
To select the current limit set point, we need to nd the
resistor value for RLIM. The current limit threshold for the
FAN5019 is set with a 3V source (VLIM) across RLIM with
a gain of 10.4mV/mA (ALIM). RLIM can be found using the
following:
For values of RLIM greater than 500k
, the current limit may
be lower than expected, so some adjustment of RLIM may be
needed. Here, ILIM is the average current limit for the output
of the supply. For our example, choosing 120A for ILIM, we
nd RLIM to be 200k
, for which we chose 200k as the
nearest 1% value.
The per phase current limit described earlier has its limit
determined by the following:
For the FAN5019, the maximum COMP voltage
(VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS)
is 1.2V, and the current balancing amplier gain (AD) is 5.
Using VR of 0.765V, and RDS(MAX) of 5.95m
(low-side
ON-resistance at 125°C), we nd a per-phase limit of 40.44A.
()
CC
GSF
SF
GMF
MF
SW
DRV
V
I
Q
n
Q
n
f
P
×
+
×
+
×
=
2
(18)
R
DS
D
R
C
R
A
L
A
R
×
=
3
(19)
=
×
×
=
k
pF
m
nH
R
291
5
95
.
5
3
650
2
.
0
()
SW
R
VID
R
f
C
R
V
D
A
V
×
×
=
1
(20)
()
V
kHz
pF
k
V
R
765
.
0
228
5
301
5
.
1
125
.
0
1
2
.
0
=
×
×
×
=
(
)
×
×
=
O
X
SW
R
RT
R
C
f
n
D
n
V
1
2
1
(21)
O
LIM
R
I
V
A
R
×
=
(22)
2
)
(
)
(
R
MAX
DS
D
BIAS
R
MAX
COMP
PHLIM
I
R
A
V
I
×
(23)
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