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参数资料
| 型号： | FAN5019MTCX_NL |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封装： | LEAD FREE, TSSOP-28 |
| 文件页数： | 15/30页 |
| 文件大小： | 781K |
| 代理商： | FAN5019MTCX_NL |
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FAN5019
PRODUCT SPECIFICATION
22
REV. 1.0.7 1/5/04
mF
F
V
m
A
nH
C
MIN
X
45
.
6
220
5
.
1
3
.
1
3
60
650
)
(
=
×
×
≥
(
)
mF
F
nH
mV
m
V
s
V
m
mV
nH
C
MAX
X
9
.
23
220
1
650
250
3
.
1
6
.
4
3
5
.
1
150
1
5
.
1
3
.
1
6
.
4
3
250
650
2
)
(
=
×
×
+
×
×
≤
where K=4.6
Using eight 820F A1-Polys with a typical ESR of 8m
,
each yields CX = 6.56F with an RX = 1.0m
. One last
check should be made to ensure that the ESL of the bulk
capacitors (LX) is low enough to limit the initial high-
frequency transient spike. This can be tested using:
In this example, LX is 375pH for the eight A1-Poly capaci-
tors, which satises this limitation. If the LX of the chosen
bulk capacitor bank is too large, the number of MLC capaci-
tors must be increased. One should note for this multi-mode
control technique, “all-ceramic” designs can be used as
long as the conditions of Equations 11, 12 and 13 are
satised.
Power MOSFETs
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches
per phase. The main selection parameters for the power
MOSFETs are VGS(TH), QG, CISS, CRSS and RDS(ON).
The minimum gate drive voltage (the supply voltage to the
FAN5009) dictates whether standard threshold or logic-level
threshold MOSFETs must be used. With VGATE ~10V,
logic-level threshold MOSFETs (VGS(TH) < 2.5V) are
recommended. The maximum output current IO determines
the RDS(ON) requirement for the low-side (synchronous)
MOSFETs. With the FAN5019, currents are balanced
between phases, thus the current in each low-side MOSFET
is the output current divided by the total number of
MOSFETs (nSF). With conduction losses being dominant,
the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and average total output
current (IO):
Knowing the maximum output current being designed for
and the maximum allowed power dissipation, one can nd
the required RDS(ON) for the MOSFET. For D-PAK
MOSFETs up to an ambient temperature of 50C, a safe
limit for PSF is 1W–1.5W at 125C junction temperature.
Thus, for our example (65A maximum), we nd RDS(SF)
(per MOSFET) < 8.7m
. This RDS(SF) is also at a junction
temperature of about 125C, so we need to make sure we
account for this when making this selection. For our exam-
ple, we selected two lower side MOSFETs at 8.6m
each at
room temperature, which gives 8.4m
at high temperature.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio
of the feedback to input needs to be small (less than 10% is
recommended), to prevent accidental turn-on of the synchro-
nous MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off
should not exceed the non-overlap dead time of the
MOSFET driver (40ns typical for the FAN5009). The
output impedance of the driver is about 2
and the typical
MOSFET input gate resistances are about 1
–2, so a total
gate capacitance of less than 6000pF should be adhered to.
Since there are two MOSFETs in parallel, we should limit
the input capacitance for each synchronous MOSFET to
3000pF.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components; conduction and switch-
ing losses. The switching loss is related to the amount of
time it takes for the main MOSFET to turn on and off, and to
the current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the switching
loss per main MOSFET, where nMF is the total number of
main MOSFETs:
Here, RG is the total gate resistance (2
for the FAN5009
and about 1
for typical high speed switching MOSFETs,
making RG = 3
) and CISS is the input capacitance of the
main MOSFET. It is interesting to note that adding more
main MOSFETs (nMF) does not really help the switching
loss per MOSFET since the additional gate capacitance
slows down switching. The best way to reduce switching
loss is to use lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following, where RDS(MF) is the ON-resistance of the
MOSFET:
2
O
R
C
L
Z
X
×
≤
(14)
()
pH
m
F
L
X
372
3
.
1
220
2
=
×
≤
(
)
(
2
12
1
SF
DS
SF
R
SF
O
SF
R
n
I
n
I
D
P
×
×
×
+
×
=
(15)
ISS
MF
G
MF
O
CC
SW
MF
S
C
n
R
n
I
V
f
P
×
= 2
)
(
(16)
)
(
2
)
(
12
1
MF
DS
MF
R
MF
O
MF
C
R
n
I
n
I
D
P
×
×
×
+
×
=
(17)
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