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| 型号： | FAN5019MTCX_NL |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封装： | LEAD FREE, TSSOP-28 |
| 文件页数： | 8/30页 |
| 文件大小： | 781K |
| 代理商： | FAN5019MTCX_NL |
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FAN5019
PRODUCT SPECIFICATION
16
REV. 1.0.7 1/5/04
inductors) to the inverting input, CSSUM. The feedback
resistor between CSCOMP and CSSUM sets the gain of the
amplier, and a lter capacitor is placed in parallel with this
resistor. The gain of the amplier is programmable by adjust-
ing the feedback resistor to set the load line required by the
microprocessor. The current information is then given as the
difference of CSREF –CSCOMP. This difference signal is
used internally to offset the VID DAC for voltage positioning
and as a differential input for the current limit comparator.
To provide the best accuracy for the sensing of current, the
CSA has been designed to have a low offset input voltage.
Also, the sensing gain is determined by external resistors so
that it can be made extremely accurate and exible.
Active Impedance Control Mode
For controlling the output voltage droop as a function of
output current, a voltage signal proportional to the total
inductor currents is created by the current sense amplier
(CSA). The ratio of this voltage to the output current is
determined by external components to allow it to be adjusted
to set the required load line. Inside the chip the CSA output
voltage is subtracted from the DAC voltage which then is
used for the reference to the error amplier. As the output
current increases the reference to the error amp decreases
causing the output voltage to decrease accordingly.
Current Control Mode and Thermal Balance
The FAN5019 has individual inputs for each phase which are
used for monitoring the current in each phase. This informa-
tion is combined with an internal ramp to create a current
balancing feedback system that has been optimized for initial
current balance accuracy and dynamic thermal balancing
during operation. This current balance information is inde-
pendent of the average output current information used for
positioning described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the sup-
ply voltage for feed-forward control for changes in the sup-
ply. A resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM
ramp. Detailed information about programming the ramp is
given in the applications section.
External resistors can be placed in series with individual
phases to create an intentional current imbalance if desired,
such as when one phase may have better cooling and can
support higher currents. Resistors RSW1 through RSW4
(see the typical application circuit in Figure 4) can be used
for adjusting FET thermal and current balance. Zero ohm
placeholder resistors should be provided in the initial layout
to allow the phase balance to be adjusted during design ne
tuning.
To increase the current in any given phase, make RSW for
that phase larger (make RSW = 0 for the hottest phase and do
not change during balancing). Increasing RSW to only 500
will make a substantial increase in phase current. Increase
each RSW value by small amounts to achieve balance,
starting with the coolest phase rst.
Voltage Control Mode
A high gain-bandwidth voltage mode error amplier is used
for the voltage-mode control loop. The control input voltage
to the positive input is set via the VID 6-bit logic code
according to the voltages listed in Table 1. This voltage is
also offset by the droop voltage for active positioning of the
output voltage as a function of current, commonly known as
active voltage positioning. The output of the amplier is the
COMP pin, which sets the termination voltage for the inter-
nal PWM ramps.
The negative input (FB) is tied to the output sense location
with a resistor RB and is used for sensing and controlling the
output voltage at this point. A current source from the FB pin
owing through RB is used for setting the no-load offset
voltage from the VID voltage. The no-load voltage will be
negative with respect to the VID DAC. The main loop com-
pensation is incorporated in the feedback network between
FB and COMP.
Soft-Start
The power-on ramp up time of the output voltage is set with
a capacitor and resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current
limit latch off time as explained in the following section. In
UVLO or when EN is a logic low, the DELAY pin is held at
ground. After the UVLO threshold is reached and EN is a
logic high, the DELAY cap is charged up with an internal
20A current source. The output voltage follows the ramp-
ing voltage on the DELAY pin, limiting the inrush current.
The soft-start time depends on the value of VID DAC and
CDLY, with a secondary effect from RDLY. Refer to the appli-
cations section for detailed information on setting CDLY.
If EN is taken low or VCC drops below UVLO, the DELAY
cap is reset to ground to be ready for another soft start cycle.
Figure 1 shows a typical start-up sequence for the FAN5019.
Over Current Limit and Latch-off Protection
The FAN5019 compares a programmable current limit set
point to the voltage from the output of the current sense
amplier. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During normal operation,
the voltage on ILIMIT is 3V. The current through the exter-
nal resistor is internally scaled to give a current limit thresh-
old of approximately 10.4mV/A. If the difference in
voltage between CSREF and CSCOMP rises above the cur-
rent limit threshold, the internal current limit amplier will
control the internal COMP voltage to maintain the average
output current at the limit.
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