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参数资料
| 型号： | FAN5019MTCX_NL |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封装： | LEAD FREE, TSSOP-28 |
| 文件页数： | 18/30页 |
| 文件大小： | 781K |
| 代理商： | FAN5019MTCX_NL |
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PRODUCT SPECIFICATION
FAN5019
REV. 1.0.7 1/5/04
25
Choosing the closest standard values for these components
yields: CA = 390pF, RA = 16.9k
, CB = 1.5nF, and CFB =
33pF.
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of
the high-side MOSFET is approximately a square wave with
a duty ratio equal to n (VOUT/VIN) and an amplitude of one-
nth of the maximum output current. To prevent large voltage
transients, a low ESR input capacitor sized for the maximum
rms current must be used. The maximum rms capacitor cur-
rent is given by:
Figure 6. Typical Transient Response for Design Example
Note that the capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes it
advisable to further derate the capacitor, or to choose a
capacitor rated at a higher temperature than required. Several
capacitors may be placed in parallel to meet size or height
requirements in the design. In this example, the input
capacitor bank is formed by three 2200F, 16V Nichicon
capacitors with a ripple current rating of 3.5A each.
To reduce the input-current di/dt to below the recommended
maximum of 0.1A/s, an additional small inductor (L > 1H
@ 15A) should be inserted between the converter and the
supply bus. That inductor also acts as a lter between the
converter and the primary power source.
Tuning Procedure for the FAN5019
DC Load line Setting
1.
Build circuit based on compensation values computed
from design spreadsheet.
2.
Hook up DC load to circuit, turn on and verify opera-
tion. Also check for jitter at no-load and full-load.
3.
Measure output voltage at no-load (VNL). Verify it is
within tolerance.
Figure 7. Efficiency vs. Output Current
(Circuit of Figure 5)
4.
Measure output voltage at full-load cold (VFLCOLD).
Let board soak for ~10 minutes at full-load and measure
output (VFLHOT). If there is a change of more than a
couple of millivolts, adjust RCS1 and RCS2 using
Equations 35 and 37.
5.
Repeat Step 4 until cold and hot voltage measurements
remain the same.
6.
Measure output voltage from no-load to full-load using
5 Amp steps. Compute the loadline slope for each
change and then average to get overall loadline slope
(ROMEAS).
7.
If ROMEAS is off from RO by more than 0.05 m
,
use the following to adjust the RPH values:
8.
Repeat Steps 6 and 7 to check loadline and repeat
adjustments if necessary.
9.
Once complete with DC loadline adjustment, do not
change RPH, RCS1, RCS2, or RTH for rest of procedure.
1
×
=
D
n
I
D
I
O
CRMS
(34)
A
I
CRMS
5
.
10
1
125
.
0
3
1
65
125
.
0
=
×
=
()
(
)
FLHOT
NL
FLCOLD
NL
OLD
CS
NEW
CS
V
R
×
=
)
(
2
)
(
2
(35)
80
100
60
40
20
0
20
040
OUTPUT CURRENT (A)
EFFICIENCY
(%)
60
10
30
50
O
OMEAS
OLD
PH
NEW
PH
R
×
=
)
(
)
(
(36)
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