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| 型号： | FDC365P |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/6页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH 35V 4.3A 6-SSOT |
| 产品变化通告： | Mold Compound Change 08/April/2008 |
| 产品目录绘图： | MOSFET SuperSOT-6 |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET P 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 35V |
| 电流 - 连续漏极(Id) @ 25° C： | 4.3A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 55 毫欧 @ 4.2A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 15nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 705pF @ 20V |
| 功率 - 最大： | 800mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 细型，TSOT-23-6 |
| 供应商设备封装： | 6-SSOT |
| 包装： | 标准包装 |
| 产品目录页面： | 1603 (CN2011-ZH PDF) |
| 其它名称： | FDC365PDKR |
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
? BV DS S
? T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = -250 μ A, V GS = 0V
I D = -250 μ A, referenced to 25°C
V DS = -28V, V GS = 0V
V GS = ±20V, V DS = 0V
-35
-26
-1
±100
V
mV / °C
μ A
nA
On Characteristics
V GS(th)
? V GS(th )
? T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = -250 μ A
I D = -250 μ A, referenced to 25°C
-1
-1.8
5.0
-3
V
mV/°C
V GS = -10V, I D = -4.2A
45
55
r DS(on)
Static Drain to Source On Resistance
V GS = -4.5V, I D = -3.2A
70
80
m ?
V GS = -10V, I D = -4.2A, T J = 125°C
69
90
g FS
Forward Transconductance
V DS = -10V, I D = -4.2A
8.7
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = -20V, V GS = 0V,
f = 1MHz
f = 1MHz
530
105
55
6.1
705
135
80
pF
pF
pF
?
Switching Characteristics
t d(on)
t r
t d(off)
t f
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
V DD = -20V, I D = -4.2A,
V GS = -10V, R GEN = 6 ?
7
3
15
3
13
10
28
10
ns
ns
ns
ns
Q g
Q g
Q gs
Total Gate Charge
Total Gate Charge
Gate to Source Charge
V GS = 0V to -10V
V GS = 0V to -5V
V DD = -20V,
I D = -4.2A
11
6
1.7
15
9
nC
nC
nC
Q gd
Gate to Drain “Miller” Charge
2.2
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0V, I S = -1.3A
(Note 2)
-0.8
-1.2
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = -4.2A, di/dt = 100A/ μ s
16
7
29
14
ns
nC
Notes :
1: R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ JA is determined by the user’s board design.
2: Pulse Test: Pulse Width < 30 0 μ s, Duty cycle < 2.0%.
a. 78°C/W when mounted on a 1
in 2 pad of 2 oz copper on FR-4
board.
b. 156°C/W when mounted on
minimum pad of 2 oz copper.
a
?2007 Fairchild Semiconductor Corporation
FDC365P Rev.C
2
www.fairchildsemi.com
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