参数资料
型号: FDD3670
厂商: Fairchild Semiconductor
文件页数: 4/5页
文件大小: 0K
描述: MOSFET N-CH 100V 34A D-PAK
产品培训模块: High Voltage Switches for Power Processing
标准包装: 2,500
系列: PowerTrench®
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 100V
电流 - 连续漏极(Id) @ 25° C: 34A
开态Rds(最大)@ Id, Vgs @ 25° C: 32 毫欧 @ 7.3A,10V
Id 时的 Vgs(th)(最大): 4V @ 250µA
闸电荷(Qg) @ Vgs: 80nC @ 10V
输入电容 (Ciss) @ Vds: 2490pF @ 50V
功率 - 最大: 1.6W
安装类型: 表面贴装
封装/外壳: TO-252-3,DPak(2 引线+接片),SC-63
供应商设备封装: TO-252
包装: 带卷 (TR)
Typical Characteristics
10
4500
8
I D = 7.3A
V DS = 20V
80V
50V
4000
3500
f = 1MHz
V GS = 0 V
3000
6
4
2
0
2500
2000
1500
1000
500
0
C ISS
C OSS
C RSS
0
10
20
30
40
50
60
0
20
40
60
80
100
200
Q g , GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
V DS , DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Capacitance Characteristics.
10000
100
10
1
THIS AREA IS
LIMITED BY r DS(on)
SINGLE PULSE
T J = MAX RATED
10 μ s
100 μ s
1 ms
1000
SINGLE PULSE
R θ JC = 1.8 o C/W
T C = 25 o C
T C = 25 C
R θ JC = 1.8 o C/W
o
CURVE BENT TO
MEASURED DATA
10 ms
DC
100
10
10
10
10
0.1
1
10
100
200
50 -5
10
-4
-3
-2
-1
1
V DS , DRAIN-SOURCE VOLTAGE (V)
Figure 9. Forward Bias Safe Operating Area.
t 1 , TIME (sec)
Figure 10. Single Pulse Maximum
Power Dissipation.
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.1
0.02
0.01
SINGLE PULSE
P DM
t 1
t 2
R θ JC = 1.8 C/W
0.01
o
NOTES:
DUTY FACTOR: D = t 1 /t 2
PEAK T J = P DM x Z θ JC x R θ JC + T C
10
10
10
10
10
0.005
-5
-4
-3
-2
-1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 11. Junction-to-Case Transient Thermal Response Curve
FDD3670 Rev C1
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