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参数资料
| 型号： | FDMA905P |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/6页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH 12V 6-MLP 2X2 |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET P 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 12V |
| 电流 - 连续漏极(Id) @ 25° C： | 10A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 16 毫欧 @ 10A，4.5V |
| Id 时的 Vgs(th)（最大）： | 1V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 29nC @ 6V |
| 输入电容 (Ciss) @ Vds： | 3405pF @ 6V |
| 功率 - 最大： | 900mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WDFN 裸露焊盘 |
| 供应商设备封装： | 6-MLP（2x2） |
| 包装： | 标准包装 |
| 其它名称： | FDMA905PFSDKR |
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DSS
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = -250 μ A, V GS = 0V
I D = -250 μ A, referenced to 25 °C
V DS = -9.6 V, V GS = 0 V
V GS = ±8 V, V DS = 0 V
-12
-4.3
-1
±100
V
mV/°C
μ A
nA
On Characteristics
V GS(th)
Δ V GS(th)
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = -250 μ A
I D = -250 μ A, referenced to 25 °C
-0.4
-0.7
2.6
-1.0
V
mV/°C
V GS = -4.5 V, I D = -10 A
14
16
r DS(on)
Static Drain to Source On Resistance
V GS = -2.5 V, I D = -8.9 A
V GS = -1.8 V, I D = -4.5 A
17
21
21
82
m Ω
V GS = -4.5 V, I D = -10 A, T J = 125 °C
16
21
g FS
Forward Transconductance
V DD = -5 V, I D = -10 A
50
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = -6 V, V GS = 0 V,
f = 1 MHz
2559
490
437
3405
735
655
pF
pF
pF
Switching Characteristics
t d(on)
Turn-On Delay Time
11
20
ns
t r
t d(off)
t f
Q g
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V DD = -6 V, I D = -10 A,
V GS = -4.5 V, R GEN = 6 Ω
V DD = -6 V, I D = -10 A,
V GS = -4.5 V
11
120
59
21
3.5
4.2
20
192
94
29
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics
V SD
t rr
Q rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V GS = 0 V, I S = -2 A
V GS = 0 V, I S = -10 A
I F = -10 A, di/dt = 100 A/ μ s
(Note 2)
(Note 2)
-0.6
-0.8
21
6.1
-1.2
-1.2
34
12
V
ns
nC
Notes:
1. R θ JA is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θ JC is guaranteed by design while R θ CA is determined by
the user's board design.
a. 52 °C/W when mounted on
a 1 in 2 pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0 %.
.
b. 145 °C/W when mounted on a
minimum pad of 2 oz copper.
?2011 Fairchild Semiconductor Corporation
FDMA905P Rev.C1
2
www.fairchildsemi.com
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