参数资料
型号: FDMB3900AN
厂商: Fairchild Semiconductor
文件页数: 4/7页
文件大小: 0K
描述: MOSFET N-CH 25V DUAL 8-MLP
标准包装: 3,000
系列: PowerTrench®
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 25V
电流 - 连续漏极(Id) @ 25° C: 7A
开态Rds(最大)@ Id, Vgs @ 25° C: 23 毫欧 @ 7A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 17nC @ 10V
输入电容 (Ciss) @ Vds: 890pF @ 13V
功率 - 最大: 800mW
安装类型: 表面贴装
封装/外壳: 8-WDFN 裸露焊盘
供应商设备封装: *
包装: 带卷 (TR)
Typical Characteristics T J = 25°C unless otherwise noted
10
900
f = 1 MHz
8
I D = 7 A
V DS = 10 V
V DS = 13 V
800
700
600
C iss
V GS = 0 V
6
500
V DS = 15 V
4
400
300
C oss
2
200
C rss
0
0
3
6
Q g , GATE CHARGE(nC)
9
12
100
0.1
1 10
V DS , DRAIN TO SOURCE VOLTAGE (V)
25
Figure 7. Gate Charge Characteristics
8
40
Figure 8. Capacitance vs Drain
to Source Voltage
6
V GS = 10 V
10
100 μ s
R θ JA = 80 C/W
4
2
o
V GS = 4.5 V
1
0.1
THIS AREA IS
LIMITED BY r DS(on)
SINGLE PULSE
T J = MAX RATED
R θ JA = 165 o C/W
T A = 25 o C
1 ms
10 ms
100 ms
1s
10 s
DC
0
25
50
75
100
125
150
0.01
0.01
0.1
1
10
100
T A , AMBIENT TEMPERATURE ( C )
o
Figure 9. Maximum Continuous Drain
Current vs Ambient Temperature
V DS , DRAIN to SOURCE VOLTAGE (V)
Figure 10. Forward Bias Safe
Operating Area
300
SINGLE PULSE
R θ JA = 165 C/W
100
o
T A = 25 C
o
10
1
10
10
10
0.5 -4
10
-3
-2
-1
1
10
100
1000
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
?2011 Fairchild Semiconductor Corporation
FDMB3900AN Rev.C3
4
www.fairchildsemi.com
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