参数资料
型号: FDMC5614P
厂商: Fairchild Semiconductor
文件页数: 2/7页
文件大小: 0K
描述: MOSFET P-CH 60V 5.7A POWER33
产品培训模块: High Voltage Switches for Power Processing
产品变化通告: Mold Compound Change 17/March/2008
产品目录绘图: 8-MLP, Power33, 56 Dual
标准包装: 1
系列: PowerTrench®
FET 型: MOSFET P 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 60V
电流 - 连续漏极(Id) @ 25° C: 5.7A
开态Rds(最大)@ Id, Vgs @ 25° C: 100 毫欧 @ 5.7A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 20nC @ 10V
输入电容 (Ciss) @ Vds: 1055pF @ 30V
功率 - 最大: 2.1W
安装类型: 表面贴装
封装/外壳: 8-PowerVDFN
供应商设备封装: 8-Power33(3x3)
包装: 标准包装
产品目录页面: 1609 (CN2011-ZH PDF)
其它名称: FDMC5614PDKR
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DS S
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = -250 μ A, V GS = 0V
I D = -250 μ A, referenced to 25°C
V DS = -48V, V GS = 0V
V GS = ±20V, V DS = 0V
-60
-54
-1
±100
V
mV/° C
μ A
nA
On Characteristics
V GS(th)
Δ V GS(th )
Δ T J
r DS(on)
g FS
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance
V GS = V DS , I D = -250 μ A
I D = -250 μ A, referenced to 25°C
V GS = -10V, I D = -5.7A
V GS = -4.5V, I D = -4.4A
V GS = -10V, I D = -5.7A , T J = 125°C
V DS = -15V, I D = -5.7A
-1
-1.95
4.7
84
108
140
11
-3
100
135
168
V
mV/°C
m Ω
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = -30V, V GS = 0V,
f = 1MHz
795
140
60
1055
185
90
pF
pF
pF
Switching Characteristics
t d(on)
t r
t d(off)
t f
Q g(TOT)
Q gs
Q gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge at 10V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V DD = -30V, I D = -1A
V GS = -10V, R GEN = 6 Ω
V GS = -10V
V DD = -30V
I D = -5.7A
10
11
32
11
15
1.6
2.7
21
23
65
22
20
2.1
3.5
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics
V SD
t rr
Q rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V GS = 0V, I S = -3.2A
I F = -3.2A, di/dt = 100A/ μ s
-0.8
-1.2
36
29
V
ns
nC
Notes:
1: R θ JA is determined with the device mounted on a 1 in 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θ JC is guaranteed by design while R θ JA is determined by the
user's board design.
(a) R θ JA = 60°C/W when mounted on a 1 in 2 pad of 2 oz copper, 1.5’x1.5’x0.062’ thick PCB.
(b) R θ JA = 135°C/W when mounted on a minimum pad of 2 oz copper.
a. 60°C/W when mounted on
a 1 in 2 pad of 2 oz copper
2: Pulse Test: Pulse Width < 30 0 μ s, Duty cycle < 2.0%.
b.135°C/W when mounted on a
minimum pad of 2 oz copper
FDMC5614P Rev.C1
2
www.fairchildsemi.com
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