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参数资料
| 型号： | FDMS3624S |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/12页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 25V DUAL 8-PQFN |
| 标准包装： | 3,000 |
| 系列： | PowerTrench® |
| FET 型： | 2 N 沟道（双）非对称型 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 25V |
| 电流 - 连续漏极(Id) @ 25° C： | 17.5A，30A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 5 毫欧 @ 17.5A，10V |
| Id 时的 Vgs(th)（最大）： | 2V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 26nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 1570pF @ 13V |
| 功率 - 最大： | 1W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-PowerTDFN |
| 供应商设备封装： | Power56 |
| 包装： | 带卷 (TR) |
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DS S
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, V GS = 0 V
I D = 1 mA, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
I D = 10 mA, referenced to 25 °C
V DS = 20 V, V GS = 0 V
V GS = 12 V/-8 V, V DS = 0 V
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
25
25
12
24
1
500
±100
±100
V
mV/°C
μ A
μ A
nA
nA
On Characteristics
V GS(th)
Δ V GS(th )
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
V GS = V DS , I D = 1 mA
I D = 250 μ A, referenced to 25 °C
I D = 10 mA, referenced to 25 °C
Q1
Q2
Q1
Q2
0.8
1.1
1.2
1.4
-4
-3
2.0
2.2
V
mV/°C
V GS = 10 V, I D = 17.5 A
3.8
5.0
V GS = 4.5 V, I D = 16 A
Q1
4.4
5.7
r DS(on)
Drain to Source On Resistance
V GS = 10 V, I D = 17.5 A,T J =125 °C
V GS = 10 V, I D = 30 A
V GS = 4.5 V, I D = 27 A
Q2
5.4
1.5
1.8
7.0
1.8
2.2
m Ω
V GS = 10 V, I D =30 A ,T J =125 °C
2.1
2.7
g FS
Forward Transconductance
V DS = 5 V, I D = 17.5 A
V DS = 5 V, I D = 30 A
Q1
Q2
100
240
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q1:
V DS = 13 V, V GS = 0 V, f = 1 MHZ
Q2:
V DS = 13 V, V GS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1570
4045
448
946
61
117
0.4
0.9
pF
pF
pF
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
Q1
Q2
7
11
ns
t r
t d(off)
t f
Q g
Q g
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q1:
V DD = 13 V, I D = 17.5 A, R GEN = 6 Ω
Q2:
V DD = 13 V, I D = 30A, R GEN = 6 Ω
V GS = 0 V to 10 V Q1
V DD = 13 V,
V GS = 0 V to 4.5 V I D = 17.5 A
Q2
V DD = 13 V,
I D = 30 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
2
5
23
39
2
4
26
59
12
27
3.3
8.2
2.7
7.6
ns
ns
ns
nC
nC
nC
nC
?2011 Fairchild Semiconductor Corporation
FDMS3624S Rev.C2
2
www.fairchildsemi.com
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