参数资料
型号: FDN352AP
厂商: Fairchild Semiconductor
文件页数: 2/5页
文件大小: 0K
描述: MOSFET P-CH 30V 1.3A SSOT-3
产品培训模块: High Voltage Switches for Power Processing
产品变化通告: Mold Compound Change 08/April/2008
产品目录绘图: SuperSOT-3, SOT-23
标准包装: 1
系列: PowerTrench®
FET 型: MOSFET P 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 30V
电流 - 连续漏极(Id) @ 25° C: 1.3A
开态Rds(最大)@ Id, Vgs @ 25° C: 180 毫欧 @ 1.3A,10V
Id 时的 Vgs(th)(最大): 2.5V @ 250µA
闸电荷(Qg) @ Vgs: 1.9nC @ 4.5V
输入电容 (Ciss) @ Vds: 150pF @ 15V
功率 - 最大: 460mW
安装类型: 表面贴装
封装/外壳: TO-236-3,SC-59,SOT-23-3
供应商设备封装: 3-SSOT
包装: 标准包装
产品目录页面: 1602 (CN2011-ZH PDF)
其它名称: FDN352APDKR
Electrical Characteristics T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
Off Characteristics
BV DSS
? BV DSS
? T J
I DSS
I GSS
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature Coef?cient
Zero Gate Voltage Drain Current
Gate–Body Leakage
V GS = 0 V, I D = –250 μ A
I D = –250 μ A, Referenced to 25 ° C
V DS = –24 V, V GS = 0 V
V GS = ± 25 V, V DS = 0 V
–30
–17
–1
± 100
V
mV/ ° C
μ A
nA
On Characteristics (Note 2)
V GS(th)
? V GS(th)
? T J
R DS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coef?cient
Static Drain–Source
V DS = V GS , I D = –250 μ A
I D = –250 μ A, Referenced to 25 ° C
V GS = –10 V, I D = –1.3 A
–0.8
–2.0
4
150
–2.5
180
V
mV/ ° C
m ?
On–Resistance
V GS = –4.5 V, I D = –1.1 A
V GS = –4.5 V, I D = –1.1 A, T J = 125 ° C
250
330
300
400
g FS
Forward Transconductance
V DS = –5 V, I D = –0.9 A
2.0
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = –15 V, V GS = 0 V, f = 1.0 MHz
150
40
20
pF
pF
pF
Switching Characteristics (Note 2)
t d(on)
t r
t d(off)
t f
Q g
Q gs
Q gd
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V DD = –10 V, I D = –1 A,
V GS = –10 V, R GEN = 6 ?
V DS = –10V, I D = –0.9 A,
V GS = –4.5 V
4
15
10
1
1.4
0.5
0.5
8
28
18
2
1.9
ns
ns
ns
ns
nC
nC
nC
Drain–Source Diode Characteristics and Maximum Ratings
I S
Maximum Continuous Drain–Source Diode Forward Current
–0.42
A
V SD
t rr
Q rr
Drain–Source Diode Forward Voltage
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
V GS = 0 V, I S = –0.42 A
I F = –3.9 A,
dI F /dt = 100 A/μs
(Note 2)
–0.8
17
7
–1.2
V
ns
nC
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is de?ned as the solder mounting
surface of the drain pins R θ JC is guaranteed by design while R θ JA is determined by the user’s board design.
(a) R θ JA = 250°C/W when mounted on a 0.02 in 2 pad of 2oz. copper.
(b) R θ JA = 270°C/W when mounted on a 0.001 in 2 pad of 2oz. copper.
2. Pulse Test: Pulse Width < 300 μ s, Duty Cycle < 2.0%
FDN352AP Rev. C1
2
www.fairchildsemi.com
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