参数资料
型号: FDS3672
厂商: Fairchild Semiconductor
文件页数: 2/7页
文件大小: 0K
描述: MOSFET N-CH 100V 7.5A 8-SOIC
产品培训模块: High Voltage Switches for Power Processing
产品变化通告: Mold Compound Change 12/Dec/2007
标准包装: 1
系列: PowerTrench®
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 100V
电流 - 连续漏极(Id) @ 25° C: 7.5A
开态Rds(最大)@ Id, Vgs @ 25° C: 23 毫欧 @ 7.5A,10V
Id 时的 Vgs(th)(最大): 4V @ 250µA
闸电荷(Qg) @ Vgs: 37nC @ 10V
输入电容 (Ciss) @ Vds: 2015pF @ 25V
功率 - 最大: 2.5W
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 标准包装
产品目录页面: 1603 (CN2011-ZH PDF)
其它名称: FDS3672DKR
Electrical Characteristics T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B VDSS
Drain to Source Breakdown Voltage
I D = 250 μ A, V GS = 0V
100
-
-
V
I DSS
I GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V DS = 80V
V GS = 0V
V GS = ± 20V
T C = 150 o C
-
-
-
-
-
-
1
250
± 100
μ A
nA
On Characteristics
V GS(TH)
Gate to Source Threshold Voltage
V GS = V DS , I D = 250 μ A
2
-
4
V
I D = 7.5A, V GS = 10V
-
0.019
0.023
r DS(ON)
Drain to Source On Resistance
I D = 6.8A, V GS = 6V
I D = 7.5A, V GS = 10V,
T C = 150 o C
-
-
0.023
0.035
0.028
0.043
?
Dynamic Characteristics
C ISS
C OSS
C RSS
Q g(TOT)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge at 10V
V DS = 25V, V GS = 0V,
f = 1MHz
V GS = 0V to 10V
-
-
-
-
2015
285
70
28
-
-
-
37
pF
pF
pF
nC
Q g(TH)
Q gs
Q gs2
Q gd
Threshold Gate Charge
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V GS = 0V to 2V
V DD = 50V
I D = 7.5A
I g = 1.0mA
-
-
-
-
4
10
6.8
6
6
-
-
-
nC
nC
nC
nC
Switching Characteristics (V GS = 10V)
t ON
t d(ON)
Turn-On Time
Turn-On Delay Time
-
-
-
14
51
-
ns
ns
t r
t d(OFF)
t f
t OFF
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
V DD = 50V, I D = 4A
V GS = 10V, R GS = 10 ?
-
-
-
-
20
37
27
-
-
-
-
96
ns
ns
ns
ns
Drain-Source Diode Characteristics
V SD
t rr
Q RR
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
I SD = 7.5A
I SD = 4A
I SD = 7.5A, dI SD /dt= 100A/ μ s
I SD = 7.5A, dI SD /dt= 100A/ μ s
-
-
-
-
-
-
-
-
1.25
1.0
55
90
V
V
ns
nC
Notes:
1: Starting T J = 25°C, L = 13mH, I AS = 8A.
2: R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. R θ JC is guaranteed by design while R θ CA is determined by the user’s board design.
3: R θ JA is measured with 1.0 in 2 copper on FR-4 board
?2012 Fairchild Semiconductor Corporation
FDS3672 Rev. C2
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