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参数资料
| 型号： | FM4005-G |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO14 |
| 封装： | GREEN, MS-012AB, SOIC-14 |
| 文件页数： | 18/23页 |
| 文件大小： | 244K |
| 代理商： | FM4005-G |
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FM4005
Rev. 2.4
Jan. 2010
Page 4 of 23
Overview
The FM4005 combines a real-time clock (RTC) and a
processor companion. The companion is a highly
integrated peripheral that
includes a processor
supervisor, a comparator used for early power-fail
warning, nonvolatile event counters, and a 64-bit
serial
number.
The
FM4005
integrates
these
functions that share a common interface in a single
package.
The real-time clock and supervisor functions are
accessed with a standard 2-wire device ID. The clock
and supervisor functions are controlled by 25 special
function registers. Some of these functions such as
the RTC and event counter circuits are maintained by
the power source on the VBAK pin, allowing them to
operate from battery or backup capacitor power when
VDD drops below an internally set threshold. Each
functional block is described below.
Processor Supervisor
Supervisors provide a host processor two basic
functions: detection of power supply fault conditions
and a watchdog timer to escape a software lockup
condition. The FM4005 has a reset pin (/RST) to
drive the processor reset input during power faults
(and power-up) and software lockups. It is an open
drain output with a weak internal pull-up to VDD.
This allows other reset sources to be wire-OR’d to
the /RST pin. When VDD is above the programmed
trip point, /RST output is pulled weakly to VDD. If
VDD drops below the reset trip point voltage level
(VTP) the /RST pin will be driven low. It will remain
low until VDD falls too low for circuit operation
which is the VRST level. When VDD rises again above
VTP, /RST will continue to drive low for at least 100
ms (tRPU) to ensure a robust system reset at a reliable
VDD level. After tRPU has been met, the /RST pin will
return to the weak high state. While /RST is asserted,
serial bus activity is locked out even if a transaction
occurred as VDD dropped below VTP. Any register
read or write operation started while VDD is above
VTP will be completed internally.
The bits VTP1 and VTP0 control the trip point of the
low voltage detect circuit. They are located in register
0Bh, bits 1 and 0. Figure 2 illustrates the reset
operation in response to the VDD voltage.
VTP
VTP1
VTP0
2.6V
0
2.9V
0
1
3.9V
1
0
4.4V
1
VDD
VTP
tRPU
RST
Figure 2. Low VDD Reset
The watchdog timer can also be used to assert the
reset signal (/RST). The watchdog is a free running
programmable timer. The period can be software
programmed from 100 ms to 3 seconds in 100 ms
increments via a 5-bit nonvolatile register. All
programmed settings are minimum values and vary
with
temperature
according
to
the
operating
specifications. The watchdog has two additional
controls associated with its operation, a watchdog
enable bit (WDE) and timer restart bits (WR). Both
the enable bit must be set and the watchdog must
timeout in order to drive /RST active. If a reset event
occurs, the timer will automatically restart on the
rising edge of the reset pulse. If not enabled, the
watchdog timer runs but has no effect on /RST. Note
that setting the maximum timeout setting (11111b)
disables the counter to save power. The second
control is a nibble that restarts the timer preventing a
reset. The timer should be restarted after changing the
timeout value.
The watchdog timeout value is located in register
0Ah, bits 4-0, the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 09h. Writing this pattern
will also cause the timer to load new timeout values.
Writing other patterns to this address will not affect
its operation. Note the watchdog timer is free-
running. Prior to enabling it, users should restart the
timer as described above. This assures that the full
timeout period will be set immediately after enabling.
The watchdog is disabled when VDD is below VTP.
The following table summarizes the watchdog bits. A
block diagram follows.
Watchdog timeout
WDT4.0
0Ah, D4-0
Watchdog enable
WDE
0Ah, D7
Watchdog restart
WR3-0
09h, D3-0
Figure 3. Watchdog Timer
Timebase
Down Counter
Watchdog
timeout
100 ms
clock
WDE
/RST
WR3-0 = 1010b
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FM4005-GTR | 功能描述:F-RAM RTC RTC Alarm Pwr Mon WDT Bat Sw RoHS:否 存储容量:512 Kbit 组织:64 K x 8 接口:SPI 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube 制造商:Cypress Semiconductor |
| FM4005-L | 制造商:FORMOSA 制造商全称:Formosa MS 功能描述:Chip Silicon Rectifier - Glass passivated type |
| FM4005M | 制造商:WEITRON 制造商全称:Weitron Technology 功能描述:Surface Mount Standard Recovery Glass Passivated Rectifiers |
| FM4005-M | 制造商:FORMOSA 制造商全称:Formosa MS 功能描述:Glass passivated type |
| FM4005MH | 制造商:WEITRON 制造商全称:Weitron Technology 功能描述:Surface Mount Standard Recovery Glass Passivated Rectifiers |
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