- 您现在的位置：买卖IC网 > PDF目录67504 > FM4005-G SPECIALTY CONSUMER CIRCUIT, PDSO14 PDF资料下载
参数资料
| 型号： | FM4005-G |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO14 |
| 封装： | GREEN, MS-012AB, SOIC-14 |
| 文件页数： | 6/23页 |
| 文件大小： | 244K |
| 代理商： | FM4005-G |
N
O
T R
EC
O
M
EN
D
ED
FO
R
N
EW
D
ES
IG
N
S
Al
te
rn
at
iv
es
: F
M
31
27
2
(5
V)
or
FM
31
L2
72
(3
V)
FM4005
Rev. 2.4
Jan. 2010
Page 14 of 23
Reserved
Reserved bits. Do not use. Should remain set to 0.
CALS
Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction from the
time-base. Calibration is explained on page 7. Nonvolatile, read/write.
CAL.4-0
These five bits control the calibration of the clock. Nonvolatile, read/write.
00h
Flags/Control
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
CF
Reserved
CAL
W
R
CF
Century Overflow Flag. This bit is set to a 1 when the values in the years register overflows from 99 to 00. This
indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record the new
century information as needed. This bit is cleared to 0 when the Flag register is read. It is read-only for the user.
Battery-backed, read/write.
CAL
Calibration Mode. When set to 1, the clock enters calibration mode. When CAL is set to 0, the clock operates
normally, and the CAL/PFO pin is controlled by the comparator. Battery-backed, read/write.
W
Write Time. Setting the W bit to 1 freezes the clock. The user can then write the timekeeping registers with
updated values. Resetting the W bit to 0 causes the contents of the time registers to be transferred to the
timekeeping counters and restarts the clock. Battery-backed, read/write.
R
Read Time. Setting the R bit to 1 copies a static image of the timekeeping core and place it into the user
registers. The user can then read them without concerns over changing values causing system errors. The R bit
going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. Battery-
backed, read/write.
Reserved
Reserved bits. Do not use. Should remain set to 0.
Two-wire Interface
The FM4005 employs an industry standard two-wire
bus that is familiar to many users. Since the FM4005
is a real-time clock and processor companion and not
a memory device, it is accessed using a unique Slave
Address (Slave ID = 1101b).
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is
controlling the bus is the master. The master is
responsible for generating the clock signal for all
operations. Any device on the bus that is being
controlled is a slave. The FM4005 is always a slave
device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. The figure
below illustrates the signal conditions that specify
the four states. Detailed timing diagrams are shown
in the electrical specifications.
Stop
(Master)
Start
(Master)
7
Data bits
(Transmitter)
6
0
Data bit
(Transmitter)
Acknowledge
(Receiver)
SCL
SDA
Figure 8. Data Transfer Protocol
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM4005 for a new operation.
If the power supply drops below the specified VTP
during operation, any 2-wire transaction in progress
will be aborted and the system must issue a Start
condition prior to performing another operation.
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations must end with a Stop condition.
相关PDF资料 |
PDF描述 |
|---|---|
| FME270-461/ES | 1 FUNCTIONS, 400 V, 1.5 A, DATA LINE FILTER |
| FME270-461V/ES | 1 FUNCTIONS, 400 V, 1.5 A, DATA LINE FILTER |
| FME270-461W/ES | 1 FUNCTIONS, 400 V, 1.5 A, DATA LINE FILTER |
| FME270-461Y/ES | 1 FUNCTIONS, 400 V, 1.5 A, DATA LINE FILTER |
| FME270-461Z/ES | 1 FUNCTIONS, 400 V, 1.5 A, DATA LINE FILTER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| FM4005-GTR | 功能描述:F-RAM RTC RTC Alarm Pwr Mon WDT Bat Sw RoHS:否 存储容量:512 Kbit 组织:64 K x 8 接口:SPI 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube 制造商:Cypress Semiconductor |
| FM4005-L | 制造商:FORMOSA 制造商全称:Formosa MS 功能描述:Chip Silicon Rectifier - Glass passivated type |
| FM4005M | 制造商:WEITRON 制造商全称:Weitron Technology 功能描述:Surface Mount Standard Recovery Glass Passivated Rectifiers |
| FM4005-M | 制造商:FORMOSA 制造商全称:Formosa MS 功能描述:Glass passivated type |
| FM4005MH | 制造商:WEITRON 制造商全称:Weitron Technology 功能描述:Surface Mount Standard Recovery Glass Passivated Rectifiers |
发布紧急采购，3分钟左右您将得到回复。