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参数资料
| 型号： | FM4005-G |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO14 |
| 封装： | GREEN, MS-012AB, SOIC-14 |
| 文件页数： | 8/23页 |
| 文件大小： | 244K |
| 代理商： | FM4005-G |
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FM4005
Rev. 2.4
Jan. 2010
Page 16 of 23
Figure 10. Single Register Write
Figure 11. Multiple Register Writes
Register Read Operation
As with writes, a read operation begins with the
Slave Address. To perform a register read, the bus
master supplies a Slave Address with the LSB set to
1. This indicates that a read operation is requested.
After receiving the complete Slave Address, the
FM4005 will begin shifting data out from the current
register address on the next clock. The address auto-
increment feature operates the same for reads as it
does for writes.
There are two types of register read operations. They
are current address read and selective address read. In
a current address read, the FM4005 uses the internal
address latch to supply the address. In a selective
read, the user performs a procedure to first set the
address to a specific value.
Current Address & Sequential Read
As mentioned above the FM4005 uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the FM4005
will begin shifting data out from the current address
on the next clock. The current address is the value
held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Each time the bus master acknowledges a byte,
this indicates that the FM4005 should read out
the next sequential byte.
There are four ways to terminate a read operation.
Failing to properly terminate the read will most likely
create a bus contention as the FM4005 attempts to
read out additional data onto the bus. The four valid
methods follow.
1.
The bus master issues a NACK in the 9
th clock
cycle and a Stop in the 10
th clock cycle. This is
illustrated
in
the
diagrams
below
and
is
preferred.
2.
The bus master issues a NACK in the 9
th clock
cycle and a Start in the 10
th.
3.
The bus master issues a Stop in the 9
th clock
cycle.
4.
The bus master issues a Start in the 9
th clock
cycle.
If the internal address reaches the top of the address
space, it will wrap around to 00h on the next read
cycle. The figures below show the proper operation
for current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
S
A
Slave Address
0
Address
A
Data Byte
A
P
By Master
Start
Address & Data
Stop
Acknowledge
00 0
By FM4005
S
A
Slave Address
Data Byte
A
P
By Master
By FM4005
Start
Address & Data
Stop
Acknowledge
Address
A
Data Byte
A
00 0 0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FM4005-GTR | 功能描述:F-RAM RTC RTC Alarm Pwr Mon WDT Bat Sw RoHS:否 存储容量:512 Kbit 组织:64 K x 8 接口:SPI 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube 制造商:Cypress Semiconductor |
| FM4005-L | 制造商:FORMOSA 制造商全称:Formosa MS 功能描述:Chip Silicon Rectifier - Glass passivated type |
| FM4005M | 制造商:WEITRON 制造商全称:Weitron Technology 功能描述:Surface Mount Standard Recovery Glass Passivated Rectifiers |
| FM4005-M | 制造商:FORMOSA 制造商全称:Formosa MS 功能描述:Glass passivated type |
| FM4005MH | 制造商:WEITRON 制造商全称:Weitron Technology 功能描述:Surface Mount Standard Recovery Glass Passivated Rectifiers |
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