参数资料
型号: FM4005-G
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO14
封装: GREEN, MS-012AB, SOIC-14
文件页数: 7/23页
文件大小: 244K
代理商: FM4005-G
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31
27
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72
(3
V)
FM4005
Rev. 2.4
Jan. 2010
Page 15 of 23
If an operation is pending when a stop is asserted,
the operation will be aborted. The master must have
control of SDA (not a memory read) in order to
assert a Stop condition.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The Acknowledge (ACK) takes place after the 8
th
data bit has been transferred in any transaction.
During this state the transmitter must release the
SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal low to acknowledge
receipt of the byte. If the receiver does not drive
SDA low, the condition is a No-Acknowledge
(NACK) and the operation is aborted.
The receiver might NACK for two distinct reasons.
First is that a byte transfer fails. In this case, the
NACK ends the current operation so that the part can
be addressed again. This allows the last byte to be
recovered in the event of a communication error.
Second and most common, the receiver does not
send an ACK to deliberately terminate an operation.
For example, during a read operation, the FM4005
will continue to place data onto the bus as long as the
receiver sends ACKs (and clocks). When a read
operation is complete and no more data is needed,
the receiver must NACK the last byte. If the receiver
ACKs the last byte, this will cause the FM4005 to
attempt to drive the bus on the next clock while the
master is sending a new command such as a Stop.
Slave Address
The first byte that the FM4005 expects after a Start
condition is the slave address. As shown in Figure 9
below, the slave address contains the Slave ID and a
bit that specifies if the transaction is a read or a
write.
The FM4005 Companion is accessed by setting bits
7-4 (Slave ID) of the slave address to 1101b.
Figure 9. Slave Address
Addressing Overview
The RTC and Processor Companion registers use
only one byte of address. Addresses 00h to 18h
correspond to special function registers. Attempting
to load an address above location 18h is an illegal
condition; the FM4005 will return a NACK and
abort the 2-wire transaction.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM4005 begins. For a read, the FM4005 will place 8
data bits on the bus then wait for an ACK from the
master. If the ACK occurs, the FM4005 will transfer
the next byte. If the ACK is not sent, the FM4005
will end the read operation. For a write operation, the
FM4005 will accept 8 data bits from the master then
send an Acknowledge. All data transfer occurs MSB
(most significant bit) first.
Register Write Operation
All register writes begin with a Slave Address, then a
register address. The bus master indicates a write
operation by setting the slave address LSB to a 0.
After addressing, the bus master sends each byte of
data to the selected register and the device generates
an
Acknowledge
condition.
Any
number
of
sequential bytes
may be
written. The device
internally increments the address for each new data
byte. If the end of the address range is reached, the
address counter will wrap to 00h. Internally, the
actual write operation occurs after the 8
th data bit is
transferred. It is completed before the Acknowledge
is sent. Therefore, if the user desires to abort a write
without altering the register contents, this should be
done using a Start or Stop condition prior to the 8
th
data bit. The figures below illustrate a single- and
multiple-writes to the RTC registers.
11
0
1
X
00
R/W
Slave ID
7
6
543
21
0
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