参数资料
| 型号： | FS6377-01IG-XTP |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN PLL PROG 16SOIC |
| 标准包装： | 3,000 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
FS6377
Table 13: AC Timing Specifications continued
Clock Outputs (PLL_C clock via CLK_C pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
100
45
55
%
Jitter, long term (
σy(τ))*
tj(LT)
On rising edges 500s apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, no other PLLs active
On rising edges 500s apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, NF= 220,
NR = 63, NPX = 50, all other PLLs active (A = 50MHz,
B = 60MHz, D = 14.318MHz)
100
40
45
105
ps
Jitter, period (peak-peak)*
tj(ΔP)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, NF= 220, NR = 63,
NPX = 50, all other PLLs active (A = 50MHz,
B = 60MHz, D = 14.318MHz)
100
40
120
440
ps
Clock Outputs (Crystal Oscillator via CLK_D pin) Approximate
Duty cycle*
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
14.318
45
55
%
Jitter, long term (
σy(τ))*
tj(LT)
On rising edges 500s apart at 2.5V relative to an
ideal clock, CL = 15pF, fXIN = 14.318MHz, no other
PLLs active
From rising edges to the next at 2.5V, CL = 15pF,
fXIN = 14.318MHz, all other PLLs active (A = 50MHz,
B = 60MHz, C = 40MHz)
14.318
20
40
ps
Jitter, period (peak-peak)*
tj(ΔP)
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL = 15pF, fXIN = 14.318MHz, all other PLLs active
(A = 50MHz, B = 60MHz, C = 40MHz)
14.318
90
450
ps
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent
nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3
σ from typical.
Table 14: Serial Interface Timing Specifications
Parameter
Symbol
Conditions/Description
Standard Mode
Units
Min.
Max.
Clock frequency
fSCL
SCL
0
100
kHz
Bus free time between STOP and
START
tBUF
4.7
s
Set-up time, START (repeated)
tsu:STA
4.7
s
Hold time, START
tnd:STA
4.0
s
Set-up time, data input
tsu:DAT
SDA
250
ns
Hold time, data input
thd:DAT
SDA
0
s
Output data valid from clock
tAA
Minimum delay to bridge undefined region of
the falling edge of SCL to avoid unintended
START or STOP
3.5
s
Rise time, data and clock
tR
SDA, SCL
1000
ns
Fall time, data and clock
tF
SDA, SCL
300
ns
High time, clock
tHI
SCL
4.0
s
Low time, clock
tLO
SCL
4.7
s
Set-up time, STOP
Tsu:STO
4.0
s
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*)
represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3
σ from typical.
Rev. 4 | Page 19 of 24 | www.onsemi.com
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