参数资料
型号: FS6377-01IG-XTP
厂商: ON Semiconductor
文件页数: 16/24页
文件大小: 0K
描述: IC CLOCK GEN PLL PROG 16SOIC
标准包装: 3,000
类型: PLL 时钟发生器
PLL:
输入: 晶体
输出: CMOS
电路数: 1
比率 - 输入:输出: 1:4
差分 - 输入:输出: 无/无
频率 - 最大: 230MHz
除法器/乘法器: 是/无
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 带卷 (TR)
FS6377
Figure 15: PLL Screen
For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as
small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a post divider of two to obtain an
optimal 50 percent duty cycle.
Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv
value in Solution #7 into post divider A and switches mux A to take the output of PLL A.
The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that
mux A has been switched to PLL A and the post divider A has the chosen 100MHz output displayed.
Repeat the steps for PLL B.
PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C and mux D are also affected
by the logic level on the SEL_CD pin, as are the post dividers C and D.
Figure 16: Post Divider Menu
Rev. 4 | Page 23 of 24 | www.onsemi.com
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