参数资料
| 型号： | FS6377-01IG-XTP |
| 厂商： | ON Semiconductor |
| 文件页数： | 21/24页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN PLL PROG 16SOIC |
| 标准包装： | 3,000 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
FS6377
4.3 Oscillator Overdrive
For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be
connected to XOUT and XIN should be left unconnected (float).
For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times and
can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01F or 0.1F capacitor. A
minimum 1V peak-to-peak signal is required to drive the internal differential oscillator buffer.
5.0 I
2C-bus Control Interface
This device is a read/write slave device meeting all Philips I
2C-bus specifications except a "general call." The bus has to be controlled
by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the
device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode
is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver.
I
2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of
VDD, while a logic-zero corresponds to ground (VSS).
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable
whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START
or STOP condition. The following bus conditions are defined by the I
2C-bus protocol.
5.1.1. Not Busy
Both the data (SDA) and clock (SLC) lines remain high to indicate the bus is not busy.
5.1.2. START Data Transfer
A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be
preceded by a START condition.
5.1.3. STOP Data Transfer
A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be
followed by a STOP condition.
5.1.4. Data Valid
The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START
condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per
data bit.
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred
between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is
overwritten to the device after the first sixteen bytes will overflow into the first register, then the second, and so on, in a first-in, first-
overwritten fashion.
Rev. 4 | Page 6 of 24 | www.onsemi.com
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