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参数资料
| 型号： | GMZAN3T |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶显示器接口控制器 |
| 文件页数： | 17/53页 |
| 文件大小： | 556K |
| 代理商： | GMZAN3T |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
24
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
4.2 Hardware Reset
Hardware Reset is performed during power-up by the internal power-on reset circuit. The power-on reset
(POR) circuit generates two signals:
RESETn: an active-low pulse of around 120ms
RESET_OUT: an active-high pulse with identical timing as RESETn; this is basically an inverted
version of RESETn. Must use 10K pull-up resistor because this is an open-drain output.
The reset signals are generated whenever the supply 3.3V voltage reaches a voltage level of +2.5V, or if
the RESETn pin is pulled low for a minimum of 160 us. A TCLK input (see Clock Requirements below)
must be applied before, during, and after the reset. While RESETn is active low, pins PD[47:10] DEN,
DHS, DVS, and DCLK are all HI-Z; HDATA [3:0], GPIO[7:0] and HFS are inputs; PBIAS and PPWR
are active outputs (0 after reset is complete). When the reset period is complete and RESETn is de-
asserted, the IC power up sequence is:
1. Reset all registers to their default state (this is 00h unless otherwise specified in the gmZAN3
Register Listing).
2. Force each clock domain to reset. Internal reset will remain asserted for 64 local clock domain cycles
following the de-assertion of RESETn.
The following figures illustrate different system configuration options of the gmZAN3 POR circuit:
1. In figure 10, the gmZAN3 RESET_OUT signal resets the external MCU during power-up. An
optional push button allows the user to reset the entire system.
2. In figure 11, an external MCU generates the reset, applied to RESETn input of gmZAN3.
DEL A Y
6K
IN T E R N A L
R E SET
2
1
R E SET _ O U T
RE S E T n
gm Z A N 3
+ 3 .3 V / + 5 V
10 K
V1
R2
R1
Po w e r
On
Re s e t
(P O R )
V2
As ta b le
M u ltiv ib r a to r
MC U
RS T
+3 .3 V
OP T IO N A L
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