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参数资料
| 型号： | GMZAN3T |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶显示器接口控制器 |
| 文件页数： | 38/53页 |
| 文件大小： | 556K |
| 代理商： | GMZAN3T |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
43
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the figure
below. A transfer is initiated (START) by a high-to-low transition on HFS while HCLK is held high. A
transfer is terminated by a STOP (a low-to-high transition on HFS while HCLK is held high) or by a
START (to begin another transfer). The HFS signal must be stable when HCLK is high, it may only
change when HCLK is low (to avoid being misinterpreted as START or STOP).
ADDRESS BYTE
HFS
123
789
HCLK
456
12
89
DATA BYTE
ACK
START
STOP
Receiver acknowledges by holding SDA low
R/W
A6
A1
A2
A3
A4
A5
A0
D6
D7
D0
Figure 26.
2-Wire Protocol Data Transfer
Each transaction on the HFS is in integer multiples of 8 bits (i.e. bytes). The number of bytes that can be
transmitted per transfer is unrestricted. Each byte is transmitted with the most significant bit (MSB) first.
After the eight data bits, the master releases the HFS line and the receiver asserts the HFS line low to
acknowledge receipt of the data. The master device generates the HCLK pulse during the acknowledge
cycle. The addressed receiver is obliged to acknowledge each byte that has been received.
The Write Address Increment and the Write Address No Increment operations allow one or multiple
registers to be programmed with only sending one start address. In Write Address Increment, the address
pointer is automatically incremented after each byte has been sent and written. The transmission data
stream for this mode is illustrated in Figure 27 below. The highlighted sections of the waveform represent
moments when the transmitting device must release the HFS line and wait for an acknowledgement from
the gmZAN3 (the slave receiver).
ACK
OPERATIONCODE
START
HFS
HCLK
STOP
DEVICEADDRESS
REGISTERADDRESS
DATA
R/W
ACK
12
34
5
6
789
12
34
5
6
789
12
3
4
5
6
789
1
2
9
A8
TwoMSBs of register address
A9
Figure 27.
2-Wire Write Operations (0x1x and 0x2x)
The Read Address Increment (0x90) and Read Address No Increment (0xA0) operations are illustrated in
Figure 28. The highlighted sections of the waveform represent moments when the transmitting device
must release the HFS line and waits for an acknowledgement from the master receiver.
Note that on the last byte read, no acknowledgement is issued to terminate the transfer.
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