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参数资料
| 型号： | GMZAN3T |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶显示器接口控制器 |
| 文件页数： | 22/53页 |
| 文件大小： | 556K |
| 代理商： | GMZAN3T |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
29
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
SCLK
Input HSync
Input Analog
Video
Phase
Delay
SDDS
BLUE
GREEN
RED
ACLK
SCLK
input HS
R
G
B
ACLK
Phase Delay
ACLK
SCLK
HS
Figure 14.
gmZAN3 Clock Recovery
4.3.4 Sampling Phase Adjustment
The programmable ADC sampling phase is adjusted by delaying the (input HSYNC aligned) SCLK to
produce the ADC clock (ACLK) inside the SDDS. The phase delay is programmable in 64 steps as a
fraction of the ACLK period. The accuracy of the sampling phase is checked and the result read from a
register. This feature enables accurate auto-adjustment of the ADC sampling phase.
4.3.5 Integrated Schmitt Trigger for Horizontal and Vertical Sync input
The gmZAN3 has integrated Schmitt triggers for Horizontal and Vertical Sync inputs, pin 85 and pin 86.
This allows for less number of components on the system board. It enables easier PCB layout, more
reliability and results in reducing the overall BOM cost.
The programmable hysteresis value is either 0.5V or 1.5V
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