
3
GP2000 – GPS CHIPSET DESIGNER’S GUIDE
GP2015 RF FRONT END
FEATURES
s L1 C/A Code Front End
s Low Voltage Operation (3V to 5V)
s Low Power Consumption (200mW at 3V)
s On-chip Phase Locked Loop including VCO
s 3-Stage Down Conversion
s 2-Bit Digital Output (Sign and Magnitude)
s 240
°C to 185°C Operating Temperature Range
s Interfaces to GP2021 Digital Correlator
s Few External Components Required
FUNCTIONAL OVERVIEW
Fig. 3 GP2015 block diagram
Fig. 3 is a block diagram of the front end integrated circuit
GP2015.
Several key blocks can be identified:
On-Chip Phase Locked Loop
Triple Down-Conversion
AGC
Power Control
On-Chip Phase locked Loop
An on-chip Phase Locked Loop (PLL) requiring only an
external 10MHz reference (01 to 12V p-p) synthesises
1400MHz which is used to generate all intermediate frequency
local oscillators for signal down-conversion. These frequencies
are 1400MHz, 140MHz and 31111MHz. An external 40MHz
clock (for use by the GP2021 correlator) is also generated. This
signal is low level differential to minimise interference.
The design has been implemented to minimise the number
of external components. The application circuit (Fig. 4) shows
the components required.
The Voltage Controlled Oscillator (VCO) has an on-chip
voltage regulator to improve noise immunity of the PLL (only
available in 5V operation).
Signal Down-Conversion
First Stage
The first stage of signal down-conversion mixes the L1 signal
at 157542MHz with a local oscillator at 14000MHz to give a
first IF of 17542MHz. This places the image at 122458MHz
(i.e. approximately L2)
The high first IF means that image attenuation can be easily
achieved with a combination of a selective antenna and a simple
low-cost filter at the antenna or input to the front end.
The first stage mixer has an image rejection filter of about
5dB (minimum) and 1dB compression point of222dBm
(minimum). Together with the selective antenna and RF filter,
this provides a good level of protection against saturation at the
input from out-of-band interfering signals.
The first IF filter is also used to suppress interfering signals
near to the IF to prevent saturation of the second stage mixer.
In practice, a typical first IF filter can be realised with discrete
components as, for example, a 2-pole coupled-tuned filter, where
a bandwidth of about 20MHz is achievable.
Second Stage
The second stage of signal down-conversion mixes the sig-
nal at 17542 MHz with a local oscillator at 1400 MHz to give a
–VR
+VR
AGC
CONTROL
RF I/P
L1
(157542
MHz)
FRONT
END
MIXER
43MHz
FILTER
IF O/P
(4309MHz)
2nd
STAGE
MIXER
14GHz
PLL
LOOP
FILTER
VCO
PHASE
DETECTOR
A-D
CONVERTER
PLL LOCK
LOGIC O/P
(LD)
175MHz FILTER
3542MHz
FILTER
40MHz CLOCK O/P
FOR CORRELATOR
CHIP (OPCLK1/2)
AGC
140MHz
3111MHz
4
5
4
7
4
4
4
2
4
9
EXT.
LOOP
FILTER
TEST
VOLTAGE
REG
PLL
REFERENCE
OSCILLATOR
PLL REF I/P
10MHz
(REF 2)
REF 1 I/P
(FOR USE WITH
CRYSTAL REF
ONLY)
32
2
3
21
27
28
37, 38
40, 41
44, 45
3rd
STAGE
MIXER
SIGN O/P
LATCH
MAG O/P
LATCH
SAMPLE
CLOCK I/P
(571MHz TTL)
SIGN O/P
(TTL)
MAG O/P
(TTL)
1400GHz
PHASE
LOCKED
LOOP
47, 48
AGC
CAPACITOR
23
24
16, 17
20
1
11
15
14
+
POWER-ON
REFERENCE
I/P (PREF)
1
121V
POWER-ON
RESET
POWER
CONTROL
POWER
DOWN I/P
POWER-ON
RESET O/P
(PRESET)
819
9