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GP2000 – GPS CHIPSET DESIGNER’S GUIDE
Carrier Cycle Counter
This block contains counters for determining the number
(whole and fractional) of in-phase carrier DCO cycles between
the last 2 TlCs.
CHx_CARRIER_CYCLE_COUNTER_HIGH and
CHx_CARRIER_CYCLE_COUNTER_LOW:
The block provides the number of positive going zero
crossings of the in-phase carrier DCO between the last 2 TlCs.
The counter is 20 bits long.
CHx_CARRIER_DCO_PHASE: gives the in-phase carrier
DCO fractional carrier phase sampled at the current TIC. The
counter is 10 bits long to give a resolution of 1/1024
(approximately 02 mm at L1 ) of a cycle.
The above registers are used to form the integrated carrier
phase measurements.
Accumulators
Four 16-bit accumulators contain the results of the code
correlation over the code period of nominally 1ms. This data
can be accessed through the following registers:
(i) CHx_I_TRACK: The accumulation from the in-phase Track arm.
(ii) CHx_Q_TRACK: The accumulation from the quadrature Track
arm.
(iii) CHx_I_PROMPT: The accumulation from the in-phase
Prompt arm.
(iv) CHx_Q_PROMPT: The accumulation from the quadrature
Prompt arm.
Fig. 10 GP2021 carrier DCO
Status Registers
There are 4 status registers, three associated with the accu-
mulators and one with the measurement data:
(i) ACCUM_STATUS_ A: Amongst other things, this
register contains a status bit for each channel which is
set when new accumulation data is available for that
channel.
(ii) ACCUM_STATUS_B: Amongst other things, this
register contains a status bit for each channel which is
set when new accumulation data becomes available
for that channel before the last accumulation result was
read. This gives an indication that the processor is not
accessing some or all of the accumulation registers at
a fast enough rate.
(iii) ACCUM_STATUS_C: This register contains a status
bit for each channel which is set or cleared according
to whether the Track arm of that channel is generating
Early or Late code when the arm is configured in Dither
mode.
(iv) MEAS_STATUS_A: Amongst other things, this register
contains a status bit for each channel which is set when
new measurement data becomes available for that
channel before the last measurement data was read.
This gives an indication that the processor is not
accessing some or all of the measurement data
registers at a fast enough rate.
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