参数资料
型号: GP2000
厂商: Mitel Networks Corporation
英文描述: ()
中文描述: ()
文件页数: 23/25页
文件大小: 256K
代理商: GP2000
7
GP2000 – GPS CHIPSET DESIGNER’S GUIDE
Fig. 8 GP2021 correlator block diagram
CORRELATOR DESCRIPTION
The GP2021 Correlator block is shown in Fig. 8; the
constituent elements are described in the following sections.
Clock Generator
The Clock Generator accepts a differential input clock,
CLK_ T/CLK_I, normally at 40MHz. From this signal it generates:
(i) Multi-phase clocks for internal use by the rest of the device.
(ii) MICRO_CLK (pin 31): a 20MHz clock with a 1:1 mark-space
ratio provided as an output for a microprocessor which has
its own memory manager/state machine.
(iii) MCLK (pin 30): a clock for the ARM60 microprocessor, which
incorporates stretched phases to implement wait-states for
the wait-state memory. This is generated by the internal
Microprocessor Interface, which is especially configured for
the ARM60 when NARMSYS (pin 4) is set low.
(iv) SAMPCLK: a 5714MHz clock for internal sampling of the
input signal and also provided as an output for possible use
by the front end as a sample clock.
Timebase Generator
The Timebase Generator generates:
(i) ACCUM_INT: a programmable interrupt which is normally
used as a trigger to access new accumulation data from the
tracking modules. The default interrupt period is 50505
s
for a master clock of 40MHz.
(ii) TIC: a signal of programmable period which is used to
sample and latch the Tracking Modules measurement data
– all at the same instant. The default TIC period is 00999999
seconds for a master clock of 40MHz.
(iii) MEAS_INT: an interrupt generated from TIC which is
normally used to access new measurement data from the
measurement data registers or as a timebase for switching
software module tasks.
Sample Latches
The input signals at SIGN0, MAG0, SIGN1 and MAG1 are
sampled (normally at 5714 MHz) and latched for distribution to
the Tracking Modules.
Bus Interface
The Bus Interface controls data transfer between the external
16-bit and the internal 32-bit data bus.
Status Registers
This block consists of four registers, three registers
containing status information relevant to the accumulation
data and one register relevant to the measurement data.
TIC
MULTIPHASE
CLOCKS
DATA
BUSES
TRACKING MODULE
CHANNEL 0
TRACKING MODULE
CHANNEL 1
TRACKING MODULE
CHANNEL 2
TRACKING MODULE
CHANNEL 11
STATUS
REGISTERS
BUS
INTERFACE
32
16
TIMEBASE
GENERATOR
SAMPLE
LATCHES
CLOCK
GENERATOR
D<15:0>
16
CLK_T
CLK_I
MICRO_CLK
SAMPCLK
SIGN0 & MAG0
SIGN1 & MAG1
MEAS_INT
ACCUM_INT
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