参数资料
| 型号： | HIP6503CBZ |
| 厂商： | Intersil |
| 文件页数： | 7/14页 |
| 文件大小： | 0K |
| 描述： | IC ACPI MULTI POWER CTRLR 20SOIC |
| 标准包装： | 380 |
| 应用： | 处理器 |
| 电流 - 电源： | 30mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 管件 |
HIP6503
1V8SB (Pin 3)
TABLE 1. 5V DUAL OUTPUT (V OUT5 ) TRUTH TABLE
This pin is the output of the internal 1.8V regulator (V OUT1 ).
This internal regulator operates for as long as 5VSB is
applied to the HIP6503. This pin is monitored for under-
voltage events.
1V8IN (Pin 2)
This pin is the input supply for the 1.8V internal regulator ’s
pass element. Connect this pin to the 3.3V DUAL /3.3V SB
output.
VCLK (Pin 6)
EN5VDL
0
0
0
0
1
1
1
S5
1
1
0
0
1
1
0
S3
1
0
1
0
1
0
1
5VDL
5V
0V
Note
0V
5V
5V
Note
COMMENTS
S0, S1 States (Active)
S3
Maintains Previous State
S4/S5
S0, S1 States (Active)
S3
Maintains Previous State
This pin is the output of the internal 2.5V clock chip regulator
(V OUT4 ). This internal regulator operates only in active
states (S0, S1/S2) and is shut off during any sleep state,
1 0 0 5V
NOTE: Combination Not Allowed.
S4/S5
regardless of the configuration of the chip. This pin is
monitored for under-voltage events.
Description
Operation
The HIP6503 controls 5 output voltages (Refer to Figures 1,
2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from an
ATX power supply. The IC is composed of three linear
controllers/regulators supplying the computer system’s
1.8V SB (V OUT1 ), 3.3V SB and PCI slots’ 3.3V AUX power
(V OUT3 ), the 2.5V RDRAM and 3.3V SDRAM memory
power (V OUT2 ), an integrated regulator dedicated to 2.5V
clock chip (V OUT4 ), a dual switch controller supplying the
5V DUAL voltage (V OUT5 ), as well as all the control and
monitoring functions necessary for complete ACPI
implementation.
Initialization
The HIP6503 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating
3.3V DUAL /3.3V SB and 1.8V SB soft-start operation shortly
after exceeding POR threshold. At 3ms (typically) after these
two outputs finish their ramp-up, the EN5VDL and MSEL
status is latched in and the chip proceeds to ramp up the
remainder of the voltages, as required.
Operational Truth Table
The EN5VDL pin offers the choice of supporting or disabling
5VDUAL output in S3 and S4/S5 sleep states. Table 1
The internal circuitry does not allow the transition from an S3
(suspend to RAM) state to an S4/S5 (suspend to disk/soft
off) state or vice versa. The only ‘legal’ transitions are from
an active state (S0, S1) to a sleep state (S3, S5) and vice
versa.
Functional Timing Diagrams
Figures 4 through 6 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN5VDL) and sleep-state pins (S3,
S5), as well as the status of the ATX supply.
5VSB
S3
S5
3.3V,
5V, 12V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 4. 5V DUAL TIMING DIAGRAM FOR EN5VDL = 1;
3.3V DUAL /3.3V SB
describes the truth combinations pertaining to this output.
The status of the EN5VDL pin can only be changed while in
active (S0, S1) states, when the bias supply (5VSB pin) is
below POR level, or during chip shutdown (SS pin shorted to
GND or within 3ms of 5VSB POR); a status change of this
pin while in a sleep state is ignored.
7
FN4882.5
July 21, 2005
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