参数资料
| 型号： | HIP6503CBZ |
| 厂商： | Intersil |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | IC ACPI MULTI POWER CTRLR 20SOIC |
| 标准包装： | 380 |
| 应用： | 处理器 |
| 电流 - 电源： | 30mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 管件 |
HIP6503
proportional to the SS (soft-start) pin voltage. As the SS pin
5VSB
S3
S5
3.3V,
5V, 12V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 5. 5V DUAL TIMING DIAGRAM FOR EN5VDL = 0;
3V DUAL /3V SB
Not shown in these diagrams is the deglitching feature used
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
5VSB
(1V/DIV)
SOFT-START
(1V/DIV)
0V
V OUT5 (5V DUAL )
V OUT1 (1.8V SB )
V OUT3 (3.3V DUAL /3.3V SB )
OUTPUT
to protect against false sleep state tripping. Both S3 and S5
pins are protected against noise by a 2 μ s filter (typically 1 -
4 μ s). This feature is useful in noisy computer environments if
the control signals have to travel over significant distances.
Additionally, the S3 pin features a 200 μ s delay in
0V
VOLTAGES
(1V/DIV)
V OUT2
(2.5V MEM )
V OUT4
(2.5V CLK )
transitioning to sleep states. Once the S3 pin goes low, an
internal timer is activated. At the end of the 200 μ s interval, if
T0 T1 T2
T3
T4
TIME
T5
the S5 pin is low, the HIP6503 switches into S5 sleep state; if
the S5 pin is high, the HIP6503 goes into S3 sleep state.
5VSB
S3
S5
3.3V,
5V, 12V
INTERNAL
VSEN 2
DEVICES
DRV2
VSEN2
DLA
VSEN1
VCLK
FIGURE 6. 2.5V MEM , 3.3V MEM , AND 2.5V CLK TIMING DIAGRAM
Soft-Start Circuit
SOFT-START INTO SLEEP STATES (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10 μ A current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
8
FIGURE 7. SOFT-START INTERVAL IN A SLEEP STATE
(ALL OUTPUTS ENABLED)
Figure 7 shows the soft-start sequence for the typical
application start-up in sleep state with all output voltages
enabled. At time T0 5VSB (bias) is applied to the circuit. At
time T1 the 5VSB surpasses POR level. An internal fast
charge circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10 μ A current source continues
the charging. The soft-start capacitor voltage reaches
approximately 1.25V at time T2, at which point the
3.3V DUAL /3.3V SB and 1.8V SB error amplifiers’ reference
inputs start their transition, resulting in the output voltages
ramping up proportionally. The ramp-up continues until time
T3 when the two voltages reach the set value. As the soft-
start capacitor voltage reaches approximately 2.75V, the
under-voltage monitoring circuit of this output is activated
and the soft-start capacitor is quickly discharged to
approximately 1.25V. Following the 3ms (typical) time-out
between T3 and T4, the MSEL and EN5VDL selections are
latched in, and the soft-start capacitor commences a second
ramp-up designed to smoothly bring up the remainder of the
voltages required by the system. At time T5 all voltages are
within regulation limits, and as the SS voltage reaches
2.75V, all the remaining UV monitors are activated and the
SS capacitor is quickly discharged to 1.25V, where it
remains until the next transition. As the 2.5V CLK output is
only active while in an active state, it does not come up, but
FN4882.5
July 21, 2005
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HIP6503CBZ-T | 功能描述:PMIC 解决方案 W/ANNEAL ACPI PWR MG T CIRCUIT 20LD RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| HIP6503CR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC |
| HIP6503EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multiple Linear Power Controller with ACPI Control Interface |
| HIP6521 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:PWM and Triple Linear Power Controller |
| HIP6521_06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:PWM and Triple Linear Power Controller |
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