参数资料
型号: HW-SPAR3-SK-UNI-G
厂商: Xilinx Inc
文件页数: 13/64页
文件大小: 0K
描述: KIT STARTER SPARTAN-3
产品变化通告: Adapter Replacement 23/May/2008
Development Systems Discontinuation 22/Jun/2009
标准包装: 1
系列: Spartan-3
类型: FPGA 配置
适用于相关产品: Spartan-3
所含物品: 面板、缆线、软件、数据表和用户手册
其它名称: 122-1521
Write Enable and Output Enable Control Signals
R
Write Enable and Output Enable Control Signals
Both 256Kx16 SRAMs share common output enable (OE#) and write enable (WE#) control
lines, as shown in Table 2-2 . These control signals also connect to the A1 Expansion
Connector (refer to “Expansion Connectors,” page 47 ).
Table 2-2:
External SRAM Control Signal Connections to Spartan-3 FPGA
Signal
OE#
WE#
FPGA Pin
K4
G3
A1 Expansion Connector Pin
18
16
SRAM Data Signals, Chip Enables, and Byte Enables
The data signals, chip enables, and byte enables are dedicated connections between the
FPGA and SRAM. Table 2-3 shows the FPGA pin connections to the SRAM designated
IC10 in Figure A-8 . Table 2-4 shows the FPGA pin connections to SRAM IC11. To disable an
SRAM, drive the associated chip enable pin High.
Table 2-3:
SRAM IC10 Connections
Signal
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
CE1 (chip enable IC10)
UB1 (upper byte enable IC10)
LB1 (lower byte enable IC10)
FPGA Pin
R1
P1
L2
J2
H1
F2
P8
D3
B1
C1
C2
R5
T5
R6
T8
N7
P7
T4
P6
A1 Expansion Connector Pin
19
17
15
13
11
9
7
5
Spartan-3 FPGA Starter Kit Board User Guide
UG130 (v1.2) June 20, 2008
13
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