参数资料
| 型号： | HW-SPAR3-SK-UNI-G |
| 厂商： | Xilinx Inc |
| 文件页数： | 29/64页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER SPARTAN-3 |
| 产品变化通告： | Adapter Replacement 23/May/2008 Development Systems Discontinuation 22/Jun/2009 |
| 标准包装： | 1 |
| 系列： | Spartan-3 |
| 类型： | FPGA 配置 |
| 适用于相关产品： | Spartan-3 |
| 所含物品： | 面板、缆线、软件、数据表和用户手册 |
| 其它名称： | 122-1521 |
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Keyboard
R
ESC
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
76
05
06
04
0C
03
0B
83
0A
01
09
78
07
E0 75
`~
1!
2@
3#
4$
5%
6^
7&
8*
9(
0)
-_
=+
Back Space
0E
TAB
16
Q
1E
W
26
E
25
R
2E
T
36
Y
3D
U
3E
I
46
O
45
P
4E
[{
55
]}
66
\|
E0 74
0D
Caps Lock
15
A
1D
S
24
D
2D
F
2C
G
35
H
3C
J
43
K
44
L
4D
;:
54
'"
5B
5D
Enter
E0 6B
58
Shift
12
1C
Z
1Z
1B
X
22
23
C
21
2B
V
2A
34
B
32
33
N
31
3B
M
3A
42
,<
41
4B
>.
49
4C
/?
4A
52
5A
Shift
59
E0 72
Ctrl
14
Alt
11
Space
29
Alt
E0 11
Ctrl
E0 14
UG130_c6_03_042404
Figure 6-3:
PS/2 Keyboard Scan Codes
The host can also send data to the keyboard. Table 6-3 provides a short list of some often-
used commands.
Table 6-3:
Common PS/2 Keyboard Commands
Command
ED
Description
Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of
an “ED” command by replying with an “FA”, after which the host sends another byte to set LED
status. The bit positions for the keyboard LEDs appear in Table 6-4 . Write a ‘1’ to the specific bit to
illuminate the associated keyboard LED.
Table 6-4: Keyboard LED Control
7
6
5
4
3
2
1
0
Ignored
Caps
Lock
Num
Lock
Scroll
Lock
EE
F3
FE
FF
Echo. Upon receiving an echo command, the keyboard replies with the same scan code “EE”.
Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA”,
after which the host sends a second byte to set the repeat rate.
Resend. Upon receiving a resend command, the keyboard resends the last scan code sent.
Reset. Resets the keyboard.
The keyboard sends data to the host only when both the data and clock lines are High, the
Idle state.
Because the host is the “bus master”, the keyboard checks whether the host is sending data
before driving the bus. The clock line can be used as a “clear to send” signal. If the host
pulls the clock line Low, the keyboard must not send any data until the clock is released.
The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by
eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’
stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to
Spartan-3 FPGA Starter Kit Board User Guide
UG130 (v1.2) June 20, 2008
29
相关PDF资料 |
PDF描述 |
|---|---|
| HW-SPAR3E-DISP-DK-UNI-G | KIT DEV SPARTAN3E DISPLAY |
| HW-SPAR3E-SK-UK-G | KIT STARTER SPARTAN-3E |
| HW-USB-II-G | PLATFORM CABLE USB II |
| HW-USBN-2A | ACCY USB DOWNLOAD CABLE STD SPD |
| HW-V4-ML401-USA | EVALUATION PLATFORM VIRTEX-4 |
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| HW-USB-2A | 功能描述:程序设计器配件 ispDOWNLOAD Cable USB Connection RoHS:否 制造商:Lattice 产品:ispDOWNLOAD Cables 用于:In-system Programming |
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