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| 型号： | HW-V4-ML410-UNI-G-J |
| 厂商： | Xilinx Inc |
| 文件页数： | 50/101页 |
| 文件大小： | 0K |
| 描述： | EVALUATION PLATFORM VIRTEX-4 |
| 产品变化通告： | Development System Discontinuation 27/Aug/2012 |
| 标准包装： | 1 |
| 系列： | Virtex®-4 |
| 类型： | FPGA |
| 适用于相关产品： | XC4VFX60-11FFG1152 |
| 所含物品： | 评估平台，小型闪存卡，DDR2 DImm，LCD 显示器 - 不包括电源 - |
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Chapter 2: ML410 Embedded Development Platform
R
Table 2-18:
GPIO LCD Control Signals from FPGA to U33
UCF Signal Name
FPGA_LCD_E
FPGA_LCD_RS
FPGA_LCD_RW
FPGA Pin (U37)
AH18
AK17
AJ17
Schematic Signal
Name
FPGA_LCD_E
FPGA_LCD_RS
FPGA_LCD_RW
LVC244 Buffer
(U33)
13
11
15
LCD I/F
(J13)
6
4
5
CPU Debugging Interfaces
ML410 platforms include two optional CPU debugging interfaces: the combined FPGA
JTAG/TRACE (P8) mictor connector and the CPU JTAG header (J12). These connectors
can be used in conjunction with third party tools, or in some cases with the Xilinx Parallel
Cable IV, to debug software as it runs on the processor. The P8 mictor connector supports
the Agilent ATC2 core that can be mapped using the ChipScope Pro CORE Generator?
software. See www.xilinx.com/chipscope for more information.
The PPC405 CPU core includes dedicated debug resources that support a variety of debug
modes for debugging during hardware and software development. These debug resources
include:
?
?
?
?
Internal debug mode for use by ROM monitors and software debuggers
External debug mode for use by JTAG debuggers
Debug wait mode, which allows the servicing of interrupts while the processor
appears to be stopped
Real-time trace mode, which supports event triggering for real-time tracing
Debug modes and events are controlled using debug registers in the processor. The debug
registers are accessed through either software running on the processor or through the
JTAG port. The debug modes, events, controls, and interfaces provide a powerful
combination of debug resources for hardware and software development tools. The JTAG
port interface supports the attachment of external debug tools, such as the ChipScope
Integrated Logic Analyzer, a tool providing logic analyzer capabilities for signals inside an
FPGA, without the need for expensive external instrumentation. Using the JTAG test
access port, a debug tool can single-step the processor and examine the internal processor
state to facilitate software debugging. This capability complies with the IEEE 1149.1
Standard for vendor-specific extensions and is, therefore, compatible with standard JTAG
hardware for Boundary-Scan system testing. See the PowerPC 405 Processor Block Reference
CPU Debug Description
External-debug mode can be used to alter normal program execution. It provides the
ability to debug both system hardware and software. External-debug mode supports
setting of multiple breakpoints, as well as monitoring processor status. Access to processor
debugging resources is available through the CPU JTAG port (J12) providing the
appropriate connections to the FPGA fabric are in place.
The PPC405 JTAG debug port in the FPGA complies with IEEE Standard 1149.1-1990, IEEE
Standard Test Access Port and Boundary Scan Architecture . This standard describes a method
for accessing internal chip resources using a four-signal or five-signal interface. The
PPC405 JTAG Debug port supports scan-based board testing and is further enhanced to
50
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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