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参数资料
| 型号： | HW-V4-ML410-UNI-G-J |
| 厂商： | Xilinx Inc |
| 文件页数： | 75/101页 |
| 文件大小： | 0K |
| 描述： | EVALUATION PLATFORM VIRTEX-4 |
| 产品变化通告： | Development System Discontinuation 27/Aug/2012 |
| 标准包装： | 1 |
| 系列： | Virtex®-4 |
| 类型： | FPGA |
| 适用于相关产品： | XC4VFX60-11FFG1152 |
| 所含物品： | 评估平台，小型闪存卡，DDR2 DImm，LCD 显示器 - 不包括电源 - |
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Detailed Description
pulse. The active-Low output of the LTC1326 pin drives the FPGA_CPU_RESET_N signal
connected to H7 on the FPGA.
In addition to resetting the CPU, SW2 can also perform a System ACE CF reset as described
in “System ACE Reset (SW1),” page 74 . This can be accomplished by simply holding down
the SW2 pushbutton for longer than two seconds. This action performs a CPU reset
followed by a System ACE CF reset. See the ML410 schematics and the LTC1236 data sheet
on the ML410 documentation CD for more details.
The front panel interface header (J23) can also drive the PB_ FPGA_CPU_RESET signal.
For more details on J23, please review the “Front Panel Interface (J23)” section.
FPGA Prog (SW4)
SW4 is a pushbutton switch for programming the FPGA.
PCI Express Clock Circuit Reset (SW5)
SW5 is a pushbutton switch that resets the PCI Express clock.
Power On/Off (SW7)
SW7 is a pushbutton power switch for the ATX power toggle circuit. Shorting pins 1 and 2
of jumper J19 allows the ATX power toggle circuit to control power on sequencing.
Switches
System ACE Configuration (SW3)
SW3 is a three position dual-inline package (DIP) switch that controls the three
configuration address pins on the System ACE CF controller. The addresses, CFGADDR0,
CFGADDR1, and CFGADDR2, are marked on SW3 as positions 1, 2, and 3 respectively.
SW3 also has an ON indicator and directional arrow etched onto the plastic housing. An
arrow appears on the board silkscreen, as well, to indicate the on position. When any of the
three switches are moved to the ON position, the associated CFGADDR bit is set to a
logic 0. When any of the three switches are moved opposite of the ON position (i.e., OFF),
the associated CFGADDR bit is set to a logic 1 via a pull-up resistor.
One side of the DIP switch is tied to pull-up resistors that are connected to each of the
CFGADDR lines while the other side of the DIP switch is connected to ground. The
configuration address lines are also connected to the front panel interface. See the “Front
of eight configurations stored on the CompactFlash card that is connected to the System
ACE device. After the user makes a valid selection on SW3, the user can then depress
pushbutton SW1 to command the System ACE device to reset and configure the FPGA
using the configuration selected by DIP switch SW3. See the System ACE CompactFlash
Solution Data Sheet [Ref 5] for more details.
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
75
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