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参数资料
型号： HW-V4-ML410-UNI-G-J
厂商： Xilinx Inc
文件页数： 74/101页
文件大小： 0K
描述： EVALUATION PLATFORM VIRTEX-4
产品变化通告： Development System Discontinuation 27/Aug/2012
标准包装： 1
系列： Virtex®-4
类型： FPGA
适用于相关产品： XC4VFX60-11FFG1152
所含物品： 评估平台，小型闪存卡，DDR2 DImm，LCD 显示器 - 不包括电源 -
Chapter 2: ML410 Embedded Development Platform
capacitors and resistors to AC-couple the signals. These connections are also shown in
Table 2-38 .
R
Table 2-38:
Connections Between FPGA and Serial ATA Connector (J25 and J26)
Signal Name
RXNPADA
RXPPADA
TXNPADA
TXPPADA
RXNPADB
RXPPADB
TXNPADB
TXPPADB
SATACLK_Q0 (1)
SATACLK_NQ0 (1)
FPGA Pin (U37)
AP25
AP26
AP22
AP23
AP17
AP18
AP20
AP21
AP29
AP28
Serial ATA Pin
J26.3
J26.2
J26.5
J26.6
J25.3
J25.2
J25.5
J25.6
-
-
Notes:
1. 300 MHz
The Serial ATA connectors have different connections to the FPGA for transmit and receive
differential pairs. The receive differential pair is connected by way of a 0.01μF capacitor to
AC-couple the incoming signal to the FPGA. The transmit differential pair between the
FPGA and the Serial ATA connector is connected by way of a 0 Ω resistor. The resistor is a
place holder to allow for AC-coupling if required at a future date.
Pushbuttons, Switches, Front Panel Interface, and Jumpers
Pushbuttons
System ACE Reset (SW1)
SW1 is a manual reset switch for the System ACE CF (U38) device. When SW1 is actuated,
it drives the PB_SYSTEM_ACE_RESET signal Low, which causes the LTC1326 (U31) to
generate a 100 μs active-Low pulse. The active-Low output from the LTC1326 drives the
reset input of the System ACE CF controller (U38) through the SYSTEMACE_RESET_N
signal. When the System ACE CF device is reset, it causes the FPGA to be reconfigured.
The ACE file used to program the device is selected via SW3 DIP switch settings.
The front panel interface header (J23) can also drive the PB_SYSTEM_ACE_RESET signal.
For more details on J23, see the “Front Panel Interface (J23)” section.
CPU Reset (SW2)
SW2 is a manual pushbutton reset switch for the PPC405 system implemented in the
FPGA. To use this switch, the user must connect the PB_FPGA_CPU_RESET signal to the
PPC405 system within the FPGA fabric. EDK provides IP to perform this task. See the EDK
Processor IP User Guide [Ref 2] for more details.
If the SW2 switch is connected in the FPGA fabric, it drives the PB_FPGA_CPU_RESET
signal Low when pushed, causing the LTC1326 (U30) to generate a 100 μs active-Low
74
www.xilinx.com
ML410 Embedded Development Platform
UG085 (v1.7.2) December 11, 2008
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