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| 型号： | HY27UG084G2M-UPIP |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | PROM |
| 英文描述： | 512M X 8 FLASH 3.3V PROM, 30 ns, PBGA52 |
| 封装： | 12 X 17 MM, 0.65 MM HEIGHT, LEAD FREE, ULGA-52 |
| 文件页数： | 8/53页 |
| 文件大小： | 438K |
| 代理商： | HY27UG084G2M-UPIP |
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Rev 0.5 / Oct. 2005
16
Preliminary
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection & Power On/Off Sequence.
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 2V(3.3V device). WP# pin provides hardware pro-
tection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is
required before internal circuit gets ready for any command sequences as shown in Figure 29. The two-step command
sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back, cache program and random read completion. The RB# pin is normally high and goes to low when the
device is busy (after a reset, read, program, erase operation). It returns to high when the internal controller has fin-
ished the operation. The pin is an open-drain driver thereby allowing two or more RB# outputs to be Or-tied. Because
pull-up resistor value is related to tr(RB#) and current drain during busy (Ibusy), an appropriate value can be obtained
with the following reference chart (Fig 30). Its value can be determined by the following guidance.
4.3 Lock Block Feature
In high state of PRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is regarded
as NAND Flash without PRE pin.
Block Lock mode is enabled while PRE pin state is high, which is to offer protection features for NAND Flash data. The
Block Lock mode is divided into Unlock, Lock, Lock-tight operation. Consecutive blocks protects data allows those
blocks to be locked or lock-tighten with no latency. This block lock scheme offers two levels of protection. The first
allows software control (command input method) of block locking that is useful for frequently changed data blocks,
while the second requires hardware control (WP# low pulse input method) before locking can be changed that is use-
ful for protecting infrequently changed code blocks. The followings summarized the locking functionality.
- All blocks are in a locked state on power-up. Unlock sequence can unlock the locked blocks.
- The Lock-tight command locks blocks and prevents from being unlocked. Lock-tight state can be returned to lock
state only by Hardware control(WP low pulse input).
1. Block lock operation
1) Lock
- Command Sequence: Lock block Command (2Ah). See Fig. 23.
- All blocks default to locked by power-up and Hardware control (WP# low pulse input)
- Partial block lock is not available; Lock block operation is based on all block unit
- Unlocked blocks can be locked by using the Lock block command, and a lock block’s status can be changed to
unlock or lock-tight using the appropriate commands
- On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10us(tLBSY)
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