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参数资料
| 型号： | HY27UG084G2M-UPIP |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | PROM |
| 英文描述： | 512M X 8 FLASH 3.3V PROM, 30 ns, PBGA52 |
| 封装： | 12 X 17 MM, 0.65 MM HEIGHT, LEAD FREE, ULGA-52 |
| 文件页数： | 9/53页 |
| 文件大小： | 438K |
| 代理商： | HY27UG084G2M-UPIP |
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Rev 0.5 / Oct. 2005
17
Preliminary
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
2) Unlock
- Command Sequence: Unlock block Command (23h) + Start block address + Command (24h) + End block address.
See Fig. 24.
- Unlocked blocks can be programmed or erased.
- An unlocked block’s status can be changed to the locked or lock-tighten state using the appropriate sequence of
commands.
- Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available.
- Start block address must be nearer to the logical LSB (Least Significant Bit) than End block address.
- One block is selected for unlocking block when Start block address is same as End block address.
3) Lock-tight
- Command Sequence: Lock-tight block Command (2Ch). See Fig. 25.
- Lock-tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. A block
that is lock-tighten can’t have its state changed by software control, only by hardware control (WP# low pulse
input); Unlocking multi area is not available
- Only locked blocks can be lock-tighten by lock-tight command.
- On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10us(tLBSY)
2. Block lock Status Read
Block Lock Status can be read on a block basis to find out whether designated block is available to be programmed or
erased. After writing 7Ah command to the command register and block address to be checked, a read cycle outputs
the content of the Block Lock Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last.
RE# or CE# does not need to be toggled for updated status. Block Lock Status Read is prohibited while the device is
busy state.
Refer to table 17 for specific Status Register definitions. The command register remains in Block Lock Status Read
mode until further commands are issued to it.
In high state of PRE pin, write protection status can be checked by Block Lock Status Read (7Ah) while
in low state by Status Read (70h).
4.4 Power-On Auto-Read (Auto-Cache read)
The device is designed to offer automatic reading of the first page without command and address input sequence dur-
ing power-on.
This feature is available in 2 possible configurations.
- Auto-Read : automatic download of page 0 block 0
- Auto-Cache read : automatic download starting from page 0 block 0. This cache read operation allows download of
any portion of memory, without any latency time.
An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin does NOT control
activation of auto- page read function. Auto-page read function is enabled only when PRE pin is logic high state. Serial
access may be done after power-on without latency. Power-On Auto Read mode is available only on 3.3V device.
Alternatively the device can support an automatic cache read download, with all same functionalities stated just above
for auto-read.
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