参数资料
型号: HY27UG084GDM-TPIS
厂商: HYNIX SEMICONDUCTOR INC
元件分类: PROM
英文描述: 512M X 8 FLASH 3.3V PROM, 30 ns, PDSO48
封装: 12 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, TSOP1-48
文件页数: 15/53页
文件大小: 438K
代理商: HY27UG084GDM-TPIS
Rev 0.5 / Oct. 2005
22
Preliminary
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
Parameter
Symbol
3.3Volt
Unit
Min
Max
CLE Setup time
tCLS
0ns
CLE Hold time
tCLH
10
ns
CE# setup time
tCS
0ns
CE# hold time
tCH
10
ns
WE# pulse width
tWP
25(3)
ns
ALE setup time
tALS
5
ns
ALE hold time
tALH
10
ns
Data setup time
tDS
20
ns
Data hold time
tDH
10
ns
Write Cycle time
tWC
50
ns
WE# High hold time
tWH
15
ns
ALE to Data Loading Time
tADL(2)
100
ns
Data Transfer from Cell to register
tR
30
us
ALE to RE# Delay
tAR
10
ns
CLE to RE# Delay
tCLR
10
ns
Ready to RE# Low
tRR
20
ns
RE# Pulse Width
tRP
25
ns
WE# High to Busy
tWB
100
ns
Read Cycle Time
tRC
50
ns
RE# Access Time
tREA
30
ns
RE# High to Output High Z
tRHZ
30
ns
CE# High to Output High Z
tCHZ
20
ns
RE# or CE# High to Output Hold
tOH
10
ns
RE# High Hold Time
tREH
15
ns
Output High Z to RE# low
tIR
0ns
CE# Access Time
tCEA
45
ns
WE# High to RE# low
tWHR
60
ns
Device Resetting Time
(Read / Program / Erase)
tRST
5/10/500(1)
us
Write Protection time
tWW(4)
100
ns
Table 12: AC Timing Characteristics
NOTE:
1
. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. tADL is the time from the WE# rising edge of final address cycle WE# rising edge of first data cycle.
3. If tCS is less than 10ns tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
4. Program / Erase Enable Operation : tWP# high to tWE# High.
Program / Erase Disable Operation : tWP# Low to tWE# High.
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