参数资料
型号: HY5PS1G421M-C4
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 1Gb DDR2 SDRAM(DDP)
中文描述: 256M X 4 DDR DRAM, 0.5 ns, PBGA63
封装: FBGA-63
文件页数: 10/79页
文件大小: 1109K
代理商: HY5PS1G421M-C4
Rev. 0.2 / Oct. 2005
10
1
HY5PS12421(L)M
HY5PS12821(L)M
Self
Idle
Setting
MRS
EMRS
Bank
Active
Precharging
Down
Writing
with
ACT
RDA
Read
SRF
REF
CKEL
MRS
CKEH
CKEH
CKEL
Write
Automatic Sequence
Command Sequence
RDA
WRA
Read
PR, PRA
PR
Refreshing
Refreshing
Down
RDA
Reading
with
Autoprecharge
WRA
Power
PPower
Reading
Writing
PR(A) = Precharge (All)
MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
CKEL = CKE low, enter Power Down
CKEH = CKE high, exit Power Down, exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions
and the commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured
in full detail.
2.1 Simplified State Diagram
All banks
precharged
Activating
CKEH
Read
Write
CKEL
CKEL
Sequence
Initialization
OCD
calibration
CKEL
CKEL
CKEL
Autoprecharge
PR, PRA
PR, PRA
2. Functional Description
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