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参数资料
| 型号： | HY5PS1G421M-C4 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA63 |
| 封装： | FBGA-63 |
| 文件页数： | 13/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G421M-C4 |
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Rev. 0.2 / Oct. 2005
13
1
HY5PS12421(L)M
HY5PS12821(L)M
1. If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD
Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of
EMRS.
2. The DDR2 SDRAM is now ready for normal operation.
*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
*2) Sequence 5 and 6 may be performed between 8 and 9.
2.3.2 Programming the Mode and Extended Mode Registers
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR)
are user defined variables and must be programmed with a Mode Register Set (MRS) command. Addition-
ally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended
strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be pro-
grammed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or
Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the
user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when
the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be
executed any time after power-up without affecting array contents.
Initialization Sequence after Power Up
tCL
tCH
/CK
CK
CKE
Command
PRE
ALL
PRE
ALL
EMRS
MRS
REF
REF
MRS
EMRS
EMRS
ANY
CMD
DLL
ENABLE
DLL
RESET
OCD
Default
OCD
CAL. MODE
EXIT
Follow OCD
Flowchart
400ns
tRFC
tRFC
tRP
tRP
tMRD
tMRD
tMRD
tOIT
min. 200 Cycle
NOP
ODT
tIS
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PDF描述 |
|---|---|
| HY5PS1G421M-E3 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821LM | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821LM-C4 | 1Gb DDR2 SDRAM(DDP) |
| HY6264A-15 | RES 2.74 KOHM 1.0 % 2010S |
| HY6264A | 8KX8-Bit CMOS SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5PS1G421M-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G431AFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431AFP-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431ALFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431ALFP-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
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