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参数资料
| 型号： | HY5PS1G421M-C4 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA63 |
| 封装： | FBGA-63 |
| 文件页数： | 28/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G421M-C4 |
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Rev. 0.2 / Oct. 2005
28
1
HY5PS12421(L)M
HY5PS12821(L)M
2.5.2 Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that define how the burst mode will operate are burst
sequence and burst length. DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst
mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for
ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the
address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write
operations are supported. Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode
operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is lim-
ited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the Burst Stop com-
mand is not supported on DDR2 SDRAM devices.
Burst Length and Sequence
Note: Page length is a function of I/O organization and column addressing
Burst Length
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
4
0 0 0
0, 1, 2, 3
0, 1, 2, 3
0 0 1
1, 2, 3, 0
1, 0, 3, 2
0 1 0
2, 3, 0, 1
2, 3, 0, 1
0 1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
0 0 1
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
0 1 0
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
0 1 1
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
1 0 0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1 0 1
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
1 1 0
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
1 1 1
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
相关PDF资料 |
PDF描述 |
|---|---|
| HY5PS1G421M-E3 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821LM | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821LM-C4 | 1Gb DDR2 SDRAM(DDP) |
| HY6264A-15 | RES 2.74 KOHM 1.0 % 2010S |
| HY6264A | 8KX8-Bit CMOS SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5PS1G421M-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G431AFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431AFP-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431ALFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431ALFP-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
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