参数资料
型号: HY5PS1G421M-C4
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 1Gb DDR2 SDRAM(DDP)
中文描述: 256M X 4 DDR DRAM, 0.5 ns, PBGA63
封装: FBGA-63
文件页数: 16/79页
文件大小: 1109K
代理商: HY5PS1G421M-C4
Rev. 0.2 / Oct. 2005
16
1
HY5PS12421(L)M
HY5PS12821(L)M
Address Field
RDQS
Extended Mode Register
DLL
0*
1
D.I.C
BA
0
A
15 ~
A
13
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
0
0
1
DLL Enable
Enable
Disable
Additive latency
A
5
0
0
0
0
1
1
1
1
A
4
0
0
1
1
0
0
1
1
A
3
0
1
0
1
0
1
0
1
Additive Latency
0
1
2
3
4
5
Reserved
Reserved
a: When Adjust mode is issued, AL from previously set value must be applied.
b: After setting to default, OCD mode needs to be exited by setting A9-A7 to
000. Refer to the following 2.2.2.3 section for detailed information
A9
0
0
0
A8
0
0
1
A7
0
1
0
OCD Calibration Program
OCD Calibration mode exit; maintain setting
Drive(1)
Drive(0)
Adjust mode
a
OCD Calibration default
b
1
0
0
1
1
1
OCD program
1
DQS
Rtt
Rtt
A1
Output Driver
Impedence Control
Normal
Half
Driver
Size
100%
60%
0
1
A10
0
1
DQS
Enable
Disable
* If RDQS is enabled, the
DM function is disabled. RDQS
is active for reads and don’t
care for writes.
A11
0
1
RDQS Enable
Disable
Enable
*1 : BA2 and A13~A15 are reserved for future use and must be programmed to 0 when setting the mode register.
BA
1
0
A6
0
0
1
1
A2
0
1
0
1
R
tt
(
NOMINAL
)
ODT Disabled
75 ohm
150 ohm
Reserved
BA1
0
0
1
1
BA0
0
1
0
1
MRS mode
MRS
EMRS(1)
EMRS(2): Reserved
EMRS(3): Reserved
BA
2
0*
1
EMRS(1) Programming
Qoff
A
12
A
12
Qoff (Optional)
a
Output buffer enabled
Output buffer disabled
a.
Outputs disabled - DQs, DQSs, DQSs,
RDQS, RDQS. This feature is used in
conjunction with DIMM IDD meaurements when
IDDQ is not desired to
be included.
0
1
A11
(RDQS Enable)
A10
(DQS Disable)
Strobe Function Matrix
RDQS/DM
RDQS
DQS
DQS
0 (Disable)
0 (Enable)
DM
Hi-z
DQS
DQS
0 (Disable)
1 (Disable)
DM
Hi-z
DQS
Hi-z
1 (Enable)
0 (Enable)
RDQS
RDQS
DQS
DQS
1 (Enable)
1 (Disable)
RDQS
Hi-z
DQS
Hi-z
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