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参数资料
| 型号： | HY5PS1G421M-E3 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 256M X 4 DDR DRAM, 0.6 ns, PBGA63 |
| 封装： | FBGA-63 |
| 文件页数： | 43/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G421M-E3 |
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Rev. 0.2 / Oct. 2005
43
1
HY5PS12421(L)M
HY5PS12821(L)M
2.7 Auto Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the
Precharge command or the auto-precharge function. When a Read or a Write command is given to the
DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank
to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If
A10 is low when the READ or WRITE command is issued, then normal Read or Write burst operation is
executed and the bank remains active at the completion of the burst sequence. If A10 is high when the
Read or Write command is issued, then the auto-precharge function is engaged. During auto-precharge, a
Read command will execute as normal with the exception that the active bank will begin to precharge on
the rising edge which is CAS latency (CL) clock cycles before the end of the read burst.
Auto-precharge is also implemented during Write commands. The precharge operation engaged by the
Auto precharge command will not begin until the last data of the burst write sequence is properly stored in
the memory array.
This feature allows the precharge operation to be partially or completely hidden during burst read cycles
(dependent upon CAS latency) thus improving system performance for random data access. The RAS
lockout circuit internally delays the Precharge operation until the array restore operation has been com-
pleted (tRAS satisfied) so that the auto precharge command may be issued with any read or write com-
mand.
Burst Read with Auto Precharge
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The
DDR2 SDRAM starts an Auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than
the read with AP command if tRAS(min) and tRTP are satisfied.
If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until
tRAS(min) is satisfied.
If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until
tRTP(min) is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge
happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read_AP
to the next Activate command becomes AL + (tRTP + tRP)* (see example 2) for BL = 8 the time from
Read_AP to the next Activate is AL + 2 + (tRTP + tRP)*, where “*” means: “rounded up to the next integer”.
In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
A new bank activate (command) may be issued to the same bank if the following two conditions are satis-
fied simultaneously.
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
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| HY6264A | 8KX8-Bit CMOS SRAM |
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相关代理商/技术参数 |
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| HY5PS1G431AFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
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| HY5PS1G431ALFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431ALFP-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431CFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
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