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参数资料
| 型号： | HY5PS1G421M-E3 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 256M X 4 DDR DRAM, 0.6 ns, PBGA63 |
| 封装： | FBGA-63 |
| 文件页数： | 8/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G421M-E3 |
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Rev. 0.2 / Oct. 2005
8
1
HY5PS12421(L)M
HY5PS12821(L)M
1.3 PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data
is referenced to the crossings of CK and CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are dis-
abled during SELF REFRESH. CKE is an SSTL_18 input, but will detect an LVCMOS LOW level
after Vdd is applied.
CS
Input
Chip Select : Enables or disables all inputs except CK, CK, CKE, DQS and DM. All commands
are masked when CS is registered high. CS provides for external bank selection on systems
with multiple banks. CS is considered part of the command code.
ODT
Input
On Die Termination Control : ODT enables on die termination resistance internal to the
DDR2 SDRAM. When enabled, on die termination is only applied to DQ, DQS, DQS, RDQS,
RDQS, and DM.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
(LDM, UDM)
Input
Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM
is sampled High coincident with that input data during a WRITE access. DM is sampled on
both edges of DQS, Although DM pins are input only, the DM loading matches the DQ and
DQS loading. For x8 device, the function of DM or RDQS/ RDQS is enabled by EMRS com-
mand.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied. Bank address also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
A0 ~ A13
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to deter-
mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs
also provide the op code during MODE REGISTER SET commands.
DQ
Input/Output
Data input / output : Bi-directional data bus
DQS, (DQS)
(UDQS),(UDQS)
(LDQS),(LDQS)
(RDQS),(RDQS)
Input/Output
Data Strobe : Output with read data, input with write data. Edge aligned with read data,
centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS cor-
responds to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be
enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and
RDQS may be used in single ended mode or paired with optional complementary signals
DQS, LDQS,UDQS and RDQS to provide differential pair signaling to the system during both
reads and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe
signals.
NC
No Connect : No internal electrical connection is present.
V
DDQ
Supply
DQ Ground
V
DDL
Supply
DLL Power Supply : 1.8V +/- 0.1V
V
SSDL
Supply
DLL Ground
VDD
Supply
Power Supply : 1.8V +/- 0.1V
V
SS
Supply
Ground
V
REF
Supply
Reference voltage for inputs for SSTL interface.
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