参数资料
型号: HY5PS1G821LM-E3
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 1Gb DDR2 SDRAM(DDP)
中文描述: 128M X 8 DDR DRAM, 0.6 ns, PBGA63
封装: FBGA-63
文件页数: 54/79页
文件大小: 1109K
代理商: HY5PS1G821LM-E3
Rev. 0.2 / Oct. 2005
54
1
HY5PS12421(L)M
HY5PS12821(L)M
Input Clock Frequency Change during Precharge Power Down
DDR2 SDRAM input clock frequency can be changed under following condition:
DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level.
A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input
clock frequency is allowed to change only within minimum and maximum operating frequency specified for the
particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels.
Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power
down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new
clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During
DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock
frequency.
CK
CKE
T0
T4
Tx+1
Ty
Ty+1
Ty+2
T1
T2
Tx
CK
Valid
DLL
RESET
NOP
200 Clocks
Frequency Change
Occurs here
Ty+3
Tz
NOP
NOP
NOP
NOP
tRP
Clock Frequency Change in Precharge Power Down Mode
tXP
tAOFD
Stable new clock
before power down exit
ODT is off during
DLL RESET
Minmum 2 clocks
required before
changing frequency
ODT
CMD
Ty+4
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