参数资料
型号: HY5PS1G821LM-E3
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 1Gb DDR2 SDRAM(DDP)
中文描述: 128M X 8 DDR DRAM, 0.6 ns, PBGA63
封装: FBGA-63
文件页数: 61/79页
文件大小: 1109K
代理商: HY5PS1G821LM-E3
Rev. 0.2 / Oct. 2005
61
1
HY5PS12421(L)M
HY5PS12821(L)M
5.2.4 Differential Input AC logic Level
1. V
IN(DC)
specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and
UDQS.
2. V
ID(DC
) specifies the input differential voltage |V
TR
-V
CP
| required for switching, where V
TR
is the true input (such as CK, DQS, LDQS
or UDQS) level and V
CP
is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to V
IH(DC)
- V
IL(DC)
.
Notes:
1. V
ID(AC)
specifies the input differential voltage |V
TR
-V
CP
| required for switching, where V
TR
is the true input signal (such as CK, DQS,
LDQS or UDQS) and V
CP
is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V
IH(AC)
- V
IL(AC)
.
2. The typical value of V
IX(AC)
is expected to be about 0.5 * VDDQ of the transmitting device and V
IX(AC)
is expected to track variations in
VDDQ . V
IX(AC)
indicates the voltage at whitch differential input signals must cross.
5.2.5 Differential AC output parameters
Notes:
1. The typical value of V
OX(AC)
is expected to be about 0.5 * V DDQ of the transmitting device and V
OX(AC
) is expected to track variations
in VDDQ . V
OX(AC)
indicates the voltage at whitch differential output signals must cross.
Symbol
Parameter
Min.
Max.
Units
Notes
V
ID
(ac)
ac differential input voltage
0.5
V
DDQ
+ 0.6
V
1
V
IX
(ac)
ac differential cross point voltage
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
Symbol
Parameter
Min.
Max.
Units
Notes
V
OX
(ac)
ac differential cross point voltage
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
V
DDQ
Crossing point
V
SSQ
V
TR
V
CP
V
ID
V
IX or
V
OX
< Differential signal levels >
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