参数资料
型号: HY5PS1G821M-E3
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 1Gb DDR2 SDRAM(DDP)
中文描述: 128M X 8 DDR DRAM, 0.6 ns, PBGA63
封装: FBGA-63
文件页数: 32/79页
文件大小: 1109K
代理商: HY5PS1G821M-E3
Rev. 0.2 / Oct. 2005
32
1
HY5PS12421(L)M
HY5PS12821(L)M
Reads interrupted by a read
Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read inter-
rupt is not allowed.
Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)
Note
1.
2.
Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write
command or Precharge command is prohibited.
Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read
burst interrupt timings are prohibited.
Read burst interruption is allowed to any bank inside DRAM.
Read burst with Auto Precharge enabled is not allowed to interrupt.
Read burst interruption is allowed by another Read with Auto Precharge command.
All command timings are referenced to burst length set in the mode register. They are not referenced
to actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst
length set in the mode register and not the actual burst (which is shorter because of interrupt).
3.
4.
5.
6.
7.
CK/CK
CMD
DQS/DQS
DQs
Read B
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
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