参数资料
型号: HY5PS1G821M-E3
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 1Gb DDR2 SDRAM(DDP)
中文描述: 128M X 8 DDR DRAM, 0.6 ns, PBGA63
封装: FBGA-63
文件页数: 73/79页
文件大小: 1109K
代理商: HY5PS1G821M-E3
Rev. 0.2 / Oct. 2005
73
1
HY5PS12421(L)M
HY5PS12821(L)M
Parameter
Symbol
DDR2-400 3-3-3
DDR2-533 4-4-4
Unit
Note
min
max
min
max
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
10
Write preamble
tWPRE
0.25
-
0.25
-
tCK
Address and control input hold
time
tIH
600
-
500
-
ps
5,7,9
Address and control input setup
time
tIS
600
-
500
-
ps
5,7,9
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to precharge command
tRAS
40*
70000
45
70000
ns
3
Active to Read or Write
(with and without Auto-Precharge)
delay
tRCD
15
-
15
-
ns
Auto-Refresh to Active/Auto-
Refresh command period
tRFC
105
-
105
-
ns
Precharge Command Period
tRP
15
-
15
-
ns
Active to Active/Auto-Refresh
command period
tRC
55*
-
60
-
ns
Active to active command period
for 1KB page size(x4,x8)
tRRD
7.5
-
7.5
-
ns
4
Active to active command period
for 2KB page size(x16)
tRRD
10
-
10
-
ns
4
CAS to CAS command delay
tCCD
2
2
tCK
Write recovery time
tWR
15
-
15
-
ns
Auto precharge write recovery +
precharge time
tDAL
WR+tRP
-
WR+tRP
-
tCK
14
Internal write to read command
delay
tWTR
2
-
2
-
tCK
Internal read to precharge
command delay
tRTP
7.5
7.5
ns
3
Exit self refresh to a non-read
command
tXSNR
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read
command
tXSRD
200
-
200
-
tCK
Exit precharge power down to any
non-read command
tXP
2
-
2
-
tCK
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