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参数资料
| 型号： | HY5R288HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 288M |
| 中文描述： | - |为2.5V | 8K的| 40 |直接RDRAM的- 288M |
| 文件页数： | 16/64页 |
| 文件大小： | 4542K |
| 代理商： | HY5R288HC |
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16
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
ROW-to-ROW Examples
Figure 10: shows examples of some of the the ROW-to-
ROW packet spacings from Table 9. A complete sequence
of activate and precharge commands is directed to a bank.
The RR8 and RR12 rules apply to this sequence. In addition
to satisfying the t
RAS
and t
RP
timing parameters, the separa-
tion between ACT commands to the same bank must also
satisfy the t
RC
timing parameter (RR4).
When a bank is activated, it is necessary for adjacent banks
to remain precharged. As a result, the adjacent banks will
also satisfy parallel timing constraints; in the example, the
RR11 and RR3 rules are analogous to the RR12 and RR4
rules.
Figure 11: shows examples of the ACT-to-ACT (RR1, RR2)
and ACT-to-PRER (RR5, RR6) command spacings from
Table 9. In general, the commands in ROW packets may be
spaced an interval t
PACKET
apart unless they are directed to
the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.
Figure 10: Row Packet Example
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ACT a0
PRER a1
t
RAS
t
RC
a0 = {Da,Ba,Ra}
a1 = {Da,Ba+1}
b0 = {Da,Ba+1,Rb}
b0 = {Da,Ba,Rb}
b0 = {Da,Ba+1,Rb}
b0 = {Da,Ba,Rb}
Same Device
Same Device
Same Device
Adjacent Bank
Adjacent Bank
Same Bank
RR7
RR3
RR4
t
RP
Same Device
Same Device
Adjacent Bank
Same Bank
RR11
RR12
ACT b0
Figure 11: Row Packet Example
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ACT a0
PRER b0
t
PACKET
ACT c0
t
RR
a0 = {Da,Ba,Ra}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
Different Device
Same Device
Different Device
Same Device
Any Bank
Non-adjacent Bank
Any Bank
Non-adjacent Bank
RR1
RR2
RR5
RR6
ACT a0
ACT a0
ACT b0
PRER c0
ACT a0
t
PACKET
t
PACKET
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