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参数资料
| 型号： | HY62EF16200ASLM-10 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | SRAM |
| 英文描述： | 128K X 16 STANDARD SRAM, 100 ns, PBGA48 |
| 封装： | MICRO, CSP, BGA-48 |
| 文件页数： | 2/13页 |
| 文件大小： | 204K |
| 代理商： | HY62EF16200ASLM-10 |
HY62UF16200A/HY62QF16200A/HY62EF16200A/HY62SF16200A Series
Rev.01 / Feb. 99
10
READ CYCLE 2(Note 1,2,4)
tRC
tAA
Data Valid
Previous Data
tOH
ADDR
Data
Out
READ CYCLE 3(Note 1,3,4)
CS
tACS
Data Valid
tCLZ(5)
tCHZ(5)
Data
Out
Notes:
1. /WE is high for the Read Cycle.
2. Device is continuously selected. /CS = VIL
3. Address valid is prior to or coincident with /CS transition low
4. /OE = VIL
5. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
WRITE CYCLE 1
ADDR
CS
Data
Out
tWC
tDW
tOHZ(3,9)
WE
Data Valid
tDH
tWP(1)
tAS
Data In
tCW
tWR(2)
tBW
tAS
tAW
UB,LB
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